Set the acq_time=6 (as in v7).
Fix large pixel calib for T=-36°C. The fix is based on IFTP data from
July 4 to July 20 with acq_time=6 and acq_time=1.
For each IX a rought estimate was obtained for the shift of the pedestal
and the 160keV pulser peaks. The shift was applied to all large pixels.
New method: step_dps.step_hist()
to generate 1D histograms.
New method: step_dps.step_sensor_main()
to return a main STEP dps_product
4keV … 64keV, 2bpo, 1s
New method: step_dps.step_sensor_aux()
to return an aux STEP dps_product
60s
1kev…2KeV, 1 bin
2keV…4keV, 7 bins
64keV… 256keV, 15 bins
256keV…384keV, 1 bin
Changed method: step_dps.assemble()
pick only LL dps_products from step.data
add two main and two aux dps_products.
Version 8.1
The `freq` argument of step_pulser was missing. The intended positional `sel`
arguments were passed as `freq`
The TESTREG write schedule collided with regular IX REG writes.
The VERSION was set in each config.*, which is not what the VERSION is
associated with. It is now set as a module attribute
solo.step.base_config.VERSION
The unused table argument scratch is now set to solo.step.base_config.SUBVERSION
There is still an optional argument version= to override.
New formal arguments: step_ppss.do_step_config(…, acq_time=1, **kwargs)
New default: step_config.ppss(…, acq_time=6, …)
The acq_time parameter tells the FPGA how many additional ADC cycles
(1µs) to wait before a digitization from the idef-x output is accepted.
The old default acq_time=1 gives a total of 2µs settling time for the
idef-x analog output. acq_time=6 extends the settling time to 7µs.
There are two digitizations per trigger. The new default adds 10µs to
the total readout time.
The readout time shall be extended to test, in orbit, if that expels the
ghosts from the haunted channels.
Extending the readout time by increasing acq_time has the least impact
on the calibration and morphology of the signal in the presence of
pileup.
Fire a test pulse to each channel at the beginning of each PHA_cadence.
The test_regs are reset every second with the usual ix config.
Each large or small pixel gets enabled in both test_regs
once during the first 16 seconds of the PHA cadence.
For the first 30 seconds of the PHA_cadence both test pulsers are fired
once per second @5000µs.
ppss_modulus learns to fire on consecutive ranges of seconds. length
must be a valid cadence, phase must be aligned to length.
New step_pixels.pixels() enumerates physical STEP pixels.
PHA_candence is set to 600s.
.do_pulser() default is enabled.
TODO? To fire 16 times instead of 30, three entries are required for
each ix:
ppss_modules(PHA_cadence, 0, 10)
ppss_modules(PHA_cadence, 10, 5)
ppss_modules(PHA_cadence, 15)
All this is untested.
