Compare commits

...
Sign in to create a new pull request.

2 commits

Author SHA1 Message Date
Stephan I. Böttcher
fa6e23d708 solo.step.ix_config: set the R bit in RSM
This implements the second option to get rid of self triggers in STEP.

Implements infrastructure in step.baseconfig and step.ppss to pass a
parameter ix_delayed_start=True to step_config.__init__().
2021-03-01 23:39:50 +01:00
Stephan I. Böttcher
55624a99af solo.step.l1l2: change default min_dt=20
STEP seems to see a lot of self-triggered events with dt < 20µs
after events deep in the landau tail.  One proposal is to raise
min dtime threshold in L2 up from 0.  This may starve the daq at very
high trigger rates but gives reliable PHA for those events that pass
the L2 trigger.

The other option is to set the I-DefX delayed startup bit, which delays
the reconnect of the shaper by 32µs after a readout.  That cannot
starve the daq, but may result in pileup and or balistic deficit errors
at high rate.

This patch adds infra to set the min_dt cut in step.ppss and
step.base_config and changes the default for all units to 20µs.
2021-03-01 23:05:00 +01:00
2 changed files with 13 additions and 8 deletions

View file

@ -27,6 +27,7 @@ class step_config(unit_config):
ix1_thr=None, ix2_thr=None, ix1_thr=None, ix2_thr=None,
temperature=-40, env='FAR', temperature=-40, env='FAR',
name = "", dp_flag=0, version=0, name = "", dp_flag=0, version=0,
min_dt=0, ix_delayed_start=True,
**kwargs): **kwargs):
if ix1_thr is None: if ix1_thr is None:
@ -77,9 +78,10 @@ class step_config(unit_config):
close = False close = False
self.ppss = step_ppss.step_ppss( self.ppss = step_ppss.step_ppss(
large=large, small=small, large=large, small=small, min_dt=min_dt,
dps = self.dps, dps = self.dps,
ix1_thr=ix1_thr, ix2_thr=ix2_thr, ix1_thr=ix1_thr, ix2_thr=ix2_thr,
ix_delayed_start=ix_delayed_start,
close=close, model=self.model) close=close, model=self.model)
else: else:
self.ppss = ppss self.ppss = ppss

View file

@ -131,7 +131,7 @@ class step_ppss(ppss_table):
for i in range(16): for i in range(16):
self += ppss_item(us, ppss_modulus(self.PHA_cadence, 7+10*i), read_sram(tag=self.TAG_PHA, a=256*i, n=256, pha=True), search=True, PHA=True) self += ppss_item(us, ppss_modulus(self.PHA_cadence, 7+10*i), read_sram(tag=self.TAG_PHA, a=256*i, n=256, pha=True), search=True, PHA=True)
def do_ix_config(self, small=True, large=True, ix1_thr=None, ix2_thr=None, ix1_test=0, ix2_test=0, **kwargs): def do_ix_config(self, small=True, large=True, ix1_thr=None, ix2_thr=None, ix1_test=0, ix2_test=0, ix_delayed_start=0, **kwargs):
if not ix1_thr: if not ix1_thr:
ix1_thr = self.ix1_thr ix1_thr = self.ix1_thr
@ -155,7 +155,10 @@ class step_ppss(ppss_table):
ix_conf_modulus = modulus_always ix_conf_modulus = modulus_always
incr = self.ix_conf_incr incr = self.ix_conf_incr
self += ppss_item(ix_config_time, ix_conf_modulus, ix_rsm(2, ix=3), IX_RSM=True) rsm=2 # Cathode readout, do not change this!
if ix_delayed_start:
rsm |= 1 # Delay analog reconnect by 36µs.
self += ppss_item(ix_config_time, ix_conf_modulus, ix_rsm(rsm, ix=3), IX_RSM=True)
self += ppss_item(ix_config_time + incr, ix_conf_modulus, ix_selfilter(2, ix=3), IX_SELFILTER=True) self += ppss_item(ix_config_time + incr, ix_conf_modulus, ix_selfilter(2, ix=3), IX_SELFILTER=True)
self += ppss_item(ix_config_time + 2*incr, ix_conf_modulus, ix_test_reg(ix1_test, ix=1), IX_TESTREG0=True) self += ppss_item(ix_config_time + 2*incr, ix_conf_modulus, ix_test_reg(ix1_test, ix=1), IX_TESTREG0=True)
self += ppss_item(ix_config_time + 3*incr, ix_conf_modulus, ix_test_reg(ix2_test, ix=2), IX_TESTREG1=True) self += ppss_item(ix_config_time + 3*incr, ix_conf_modulus, ix_test_reg(ix2_test, ix=2), IX_TESTREG1=True)
@ -166,15 +169,15 @@ class step_ppss(ppss_table):
thrs_us1 = thrs_us0 + 2 * incr + 2 * incr thrs_us1 = thrs_us0 + 2 * incr + 2 * incr
self += ppss_items(thrs_us1, ix_conf_modulus, ix_thresholds(ix2_thr, ix=2),incr=incr, IX_THR1=True) self += ppss_items(thrs_us1, ix_conf_modulus, ix_thresholds(ix2_thr, ix=2),incr=incr, IX_THR1=True)
def do_step_config(self, small=True, large=True): def do_step_config(self, small=True, large=True, min_dt=0, **kwargs):
conf_us = 1400 conf_us = 1400
step_conf_modulus = modulus_always step_conf_modulus = modulus_always
if not large: if not large:
self += ppss_item(conf_us, step_conf_modulus, step_config_l1_l2(max_large=0, max_small=15, max_bg=1, max_sum=16, min_dt=0, read_delay=24), L1L2=True) self += ppss_item(conf_us, step_conf_modulus, step_config_l1_l2(max_large=0, max_small=15, max_bg=1, max_sum=16, min_dt=min_dt, read_delay=24), L1L2=True)
elif not small: elif not small:
self += ppss_item(conf_us, step_conf_modulus, step_config_l1_l2(max_large=15, max_small=0, max_bg=1, max_sum=16, min_dt=0, read_delay=24), L1L2=True) self += ppss_item(conf_us, step_conf_modulus, step_config_l1_l2(max_large=15, max_small=0, max_bg=1, max_sum=16, min_dt=min_dt, read_delay=24), L1L2=True)
else: else:
self += ppss_item(conf_us, step_conf_modulus, step_config_l1_l2(max_large=15, max_small=15, max_bg=2, max_sum=32, min_dt=0, read_delay=24), L1L2=True) self += ppss_item(conf_us, step_conf_modulus, step_config_l1_l2(max_large=15, max_small=15, max_bg=2, max_sum=32, min_dt=min_dt, read_delay=24), L1L2=True)
self += ppss_item(conf_us+10, step_conf_modulus, step_config_all_acq(all=(0,0), acq=(1,5)), ALLACQ=True) self += ppss_item(conf_us+10, step_conf_modulus, step_config_all_acq(all=(0,0), acq=(1,5)), ALLACQ=True)
def make_HK_table(self): def make_HK_table(self):
@ -219,7 +222,7 @@ class step_ppss(ppss_table):
self.do_init() self.do_init()
self.do_insertion_slots() self.do_insertion_slots()
self.do_ix_config(small=small, large=large, **kwargs) self.do_ix_config(small=small, large=large, **kwargs)
self.do_step_config(small=small, large=large) self.do_step_config(small=small, large=large, **kwargs)
self.do_hk() self.do_hk()
self.do_pha() self.do_pha()
if self.dps: if self.dps: