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2 commits
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fa6e23d708 | ||
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55624a99af |
2 changed files with 13 additions and 8 deletions
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@ -27,6 +27,7 @@ class step_config(unit_config):
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ix1_thr=None, ix2_thr=None,
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temperature=-40, env='FAR',
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name = "", dp_flag=0, version=0,
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min_dt=0, ix_delayed_start=True,
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**kwargs):
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if ix1_thr is None:
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@ -77,9 +78,10 @@ class step_config(unit_config):
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close = False
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self.ppss = step_ppss.step_ppss(
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large=large, small=small,
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large=large, small=small, min_dt=min_dt,
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dps = self.dps,
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ix1_thr=ix1_thr, ix2_thr=ix2_thr,
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ix_delayed_start=ix_delayed_start,
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close=close, model=self.model)
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else:
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self.ppss = ppss
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@ -131,7 +131,7 @@ class step_ppss(ppss_table):
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for i in range(16):
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self += ppss_item(us, ppss_modulus(self.PHA_cadence, 7+10*i), read_sram(tag=self.TAG_PHA, a=256*i, n=256, pha=True), search=True, PHA=True)
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def do_ix_config(self, small=True, large=True, ix1_thr=None, ix2_thr=None, ix1_test=0, ix2_test=0, **kwargs):
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def do_ix_config(self, small=True, large=True, ix1_thr=None, ix2_thr=None, ix1_test=0, ix2_test=0, ix_delayed_start=0, **kwargs):
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if not ix1_thr:
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ix1_thr = self.ix1_thr
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@ -155,7 +155,10 @@ class step_ppss(ppss_table):
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ix_conf_modulus = modulus_always
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incr = self.ix_conf_incr
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self += ppss_item(ix_config_time, ix_conf_modulus, ix_rsm(2, ix=3), IX_RSM=True)
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rsm=2 # Cathode readout, do not change this!
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if ix_delayed_start:
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rsm |= 1 # Delay analog reconnect by 36µs.
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self += ppss_item(ix_config_time, ix_conf_modulus, ix_rsm(rsm, ix=3), IX_RSM=True)
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self += ppss_item(ix_config_time + incr, ix_conf_modulus, ix_selfilter(2, ix=3), IX_SELFILTER=True)
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self += ppss_item(ix_config_time + 2*incr, ix_conf_modulus, ix_test_reg(ix1_test, ix=1), IX_TESTREG0=True)
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self += ppss_item(ix_config_time + 3*incr, ix_conf_modulus, ix_test_reg(ix2_test, ix=2), IX_TESTREG1=True)
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@ -166,15 +169,15 @@ class step_ppss(ppss_table):
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thrs_us1 = thrs_us0 + 2 * incr + 2 * incr
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self += ppss_items(thrs_us1, ix_conf_modulus, ix_thresholds(ix2_thr, ix=2),incr=incr, IX_THR1=True)
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def do_step_config(self, small=True, large=True):
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def do_step_config(self, small=True, large=True, min_dt=0, **kwargs):
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conf_us = 1400
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step_conf_modulus = modulus_always
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if not large:
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self += ppss_item(conf_us, step_conf_modulus, step_config_l1_l2(max_large=0, max_small=15, max_bg=1, max_sum=16, min_dt=0, read_delay=24), L1L2=True)
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self += ppss_item(conf_us, step_conf_modulus, step_config_l1_l2(max_large=0, max_small=15, max_bg=1, max_sum=16, min_dt=min_dt, read_delay=24), L1L2=True)
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elif not small:
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self += ppss_item(conf_us, step_conf_modulus, step_config_l1_l2(max_large=15, max_small=0, max_bg=1, max_sum=16, min_dt=0, read_delay=24), L1L2=True)
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self += ppss_item(conf_us, step_conf_modulus, step_config_l1_l2(max_large=15, max_small=0, max_bg=1, max_sum=16, min_dt=min_dt, read_delay=24), L1L2=True)
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else:
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self += ppss_item(conf_us, step_conf_modulus, step_config_l1_l2(max_large=15, max_small=15, max_bg=2, max_sum=32, min_dt=0, read_delay=24), L1L2=True)
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self += ppss_item(conf_us, step_conf_modulus, step_config_l1_l2(max_large=15, max_small=15, max_bg=2, max_sum=32, min_dt=min_dt, read_delay=24), L1L2=True)
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self += ppss_item(conf_us+10, step_conf_modulus, step_config_all_acq(all=(0,0), acq=(1,5)), ALLACQ=True)
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def make_HK_table(self):
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@ -219,7 +222,7 @@ class step_ppss(ppss_table):
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self.do_init()
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self.do_insertion_slots()
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self.do_ix_config(small=small, large=large, **kwargs)
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self.do_step_config(small=small, large=large)
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self.do_step_config(small=small, large=large, **kwargs)
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self.do_hk()
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self.do_pha()
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if self.dps:
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