New formal arguments: step_ppss.do_step_config(…, acq_time=1, **kwargs)
New default: step_config.ppss(…, acq_time=6, …)
The acq_time parameter tells the FPGA how many additional ADC cycles
(1µs) to wait before a digitization from the idef-x output is accepted.
The old default acq_time=1 gives a total of 2µs settling time for the
idef-x analog output. acq_time=6 extends the settling time to 7µs.
There are two digitizations per trigger. The new default adds 10µs to
the total readout time.
The readout time shall be extended to test, in orbit, if that expels the
ghosts from the haunted channels.
Extending the readout time by increasing acq_time has the least impact
on the calibration and morphology of the signal in the presence of
pileup.
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