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528bdf7208 ... a9f04a9b32

Author SHA1 Message Date
Stephan I. Böttcher
a9f04a9b32 sch text fix 2024-01-23 00:44:44 +01:00
Stephan I. Böttcher
85cbf8e95a updi232: power via DTR, finishing touches 2024-01-23 00:15:01 +01:00
10 changed files with 654 additions and 411 deletions
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1
.gitignore vendored
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@ -12,3 +12,4 @@ gerber/*.pdf
gerber/*.png gerber/*.png
*.save *.save
fp.py fp.py
__pycache__/

11
fp/SOT23_5.fp Normal file
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@ -0,0 +1,11 @@
Element["" "SOT23_5" "U?" "unknown" 0 0 0 0 0 50 ""] (
Pad[-1mm -0.95mm -1.4mm -0.95mm 0.6mm 20mil 0.7524mm "" "1" "square"]
Pad[-1mm 0mm -1.4mm 0mm 0.6mm 20mil 0.7524mm "" "2" "square"]
Pad[-1mm 0.95mm -1.4mm 0.95mm 0.6mm 20mil 0.7524mm "" "3" "square"]
Pad[1mm 0.95mm 1.4mm 0.95mm 0.6mm 20mil 0.7524mm "" "4" "square"]
Pad[1mm -0.95mm 1.4mm -0.95mm 0.6mm 20mil 0.7524mm "" "5" "square"]
ElementLine[-1mm -1.425mm -1mm 1.425mm 5mil]
ElementLine[-1mm 1.425mm 1mm 1.425mm 5mil]
ElementLine[1mm 1.425mm 1mm -1.425mm 5mil]
ElementLine[1mm -1.425mm -1mm -1.425mm 5mil]
)

1
fp/SUBD9_F.fp
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@ -10,6 +10,7 @@ Element["" "SUBD9_F" "U?" "unknown" 0 0 0 0 0 50 ""] (
Pin[-1.42mm -4.155mm 2.008mm 20mil 2.1604mm 1mm "" "9" ""] Pin[-1.42mm -4.155mm 2.008mm 20mil 2.1604mm 1mm "" "9" ""]
Pin[0 -486mil 250mil 20mil 256mil 125mil "" "10" ""] Pin[0 -486mil 250mil 20mil 256mil 125mil "" "10" ""]
Pin[0 486mil 250mil 20mil 256mil 125mil "" "11" ""] Pin[0 486mil 250mil 20mil 256mil 125mil "" "11" ""]
ElementLine[-9.52mm 5.54mm -9.52mm -5.54mm 5mil]
ElementLine[2.84mm 6.925mm 2.84mm -6.925mm 5mil] ElementLine[2.84mm 6.925mm 2.84mm -6.925mm 5mil]
ElementLine[2.84mm -6.925mm -2.84mm -6.925mm 5mil] ElementLine[2.84mm -6.925mm -2.84mm -6.925mm 5mil]
ElementLine[-2.84mm -6.925mm -2.84mm 6.925mm 5mil] ElementLine[-2.84mm -6.925mm -2.84mm 6.925mm 5mil]

4
make-fp.py
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@ -4,9 +4,9 @@ from fp import *
make(SOIC, (16,)) make(SOIC, (16,))
make(HEADER, (2,6,)) make(HEADER, (2,6,))
make(SOT, (3,)) make(SOT, (3,5))
make(SC70, (6,)) make(SC70, (6,))
part(SUBD, n=9, sex="F", female=True) part(SUBD, n=9, sex="F", female=True, backset=8.1*mm)
part(SOD, partname="SOD123") part(SOD, partname="SOD123")
part(SOD, partname="SOD523", polar=2) part(SOD, partname="SOD523", polar=2)
part(SOD, partname="C0603") part(SOD, partname="C0603")

60
updi232.net
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@ -1,34 +1,40 @@
unnamed_net16 R20-2 R21-2 Q2-5 unnamed_net10 J30-1 R33-1
unnamed_net15 R10-2 Q2-2 BYP C30-2 R30-1 U30-3
unnamed_net14 R21-1 R12-1 Q2-6 ADJ_CC R32-2 R31-1 U30-4
unnamed_net13 R16-1 Q4-2 DTR R33-2 C31-1 R30-2 U30-1
unnamed_net12 Q4-6 R17-1 Q4-5 unnamed_net9 R20-2 R21-2 Q2-5
unnamed_net11 R11-2 Q3-2 unnamed_net8 R10-2 Q2-2
unnamed_net10 Q3-5 R15-1 Q3-6 unnamed_net7 R21-1 R12-1 Q2-6
unnamed_net9 R14-1 Q1-3 unnamed_net6 R16-1 Q4-2
unnamed_net8 Q2-3 R13-1 Q1-1 unnamed_net5 Q4-6 R17-1 Q4-5
UPDI R16-2 Q3-3 R14-2 J1-5 unnamed_net4 R11-2 Q3-2
unnamed_net7 R5-2 D6-1 unnamed_net3 Q3-5 R15-1 Q3-6
unnamed_net6 R6-2 D7-1 unnamed_net2 R14-1 Q1-3
unnamed_net5 R2-2 D2-1 unnamed_net1 Q2-3 R13-1 Q1-1
unnamed_net4 R3-2 D3-1 VccT C12-1 R7-1 J2-2 J1-2
unnamed_net3 D6-2 D7-2 C7-2 D4-2 R4-1 UPDI R16-2 Q3-3 R14-2 J1-1
D6a R5-2 D6-1
D7a R6-2 D7-1
D2a R2-2 D2-1
D3a R3-2 D3-1
D4k D6-2 D7-2 C7-2 D4-2 R4-1
V12V R13-2 Q1-2 D8-2 D2-2 D3-2 C8-1 D5-2 V12V R13-2 Q1-2 D8-2 D2-2 D3-2 C8-1 D5-2
unnamed_net2 R4-2 C5-1 D5-1 D5a R4-2 C5-1 D5-1
unnamed_net1 D4-1 C6-1 D1-2 D4a D4-1 C6-1 D1-2
Vcc C11-1 C12-1 C13-1 R12-2 R18-2 R17-2 R15-2 J1-2 R6-1 R3-1 U1-16 Vcc J2-1 C30-1 R31-2 U30-5 C11-1 C13-1 R12-2 R18-2 R17-2 R15-2 R6-1 R3-1 U1-16
MC1+ C5-2 C1-2 U1-1 MC1+ C5-2 C1-2 U1-1
CTS R20-1 R10-1 U1-12 RTS R20-1 R10-1 U1-12
TxD R18-1 Q4-3 U1-11 RxD R18-1 Q4-3 U1-11
RTS U1-10 CTS R7-2 U1-10
RxD R11-1 U1-9 TxD R11-1 U1-9
MV- C4-1 U1-6 MV- C4-1 U1-6
MC2- C6-2 C2-1 U1-5 MC2- C6-2 C2-1 U1-5
MC2+ D1-1 C2-2 U1-4 MC2+ D1-1 C2-2 U1-4
MC1- C1-1 U1-3 MC1- C1-1 U1-3
MV+ R5-1 R2-1 R1-1 C3-1 U1-2 MV+ R5-1 R2-1 R1-1 C3-1 U1-2
TxDD U1-14 CONN1-2 RxDD U1-14 CONN1-2
CTSD U1-13 CONN1-7 RTSD U1-13 CONN1-7
RxDD U1-8 CONN1-3 TxDD U1-8 CONN1-3
RTSD U1-7 CONN1-8 CTSD U1-7 CONN1-8
GND C11-2 C12-2 C13-2 Q2-4 Q2-1 Q4-1 Q4-4 Q3-4 Q3-1 J1-6 D8-1 C7-1 C8-2 BOARD-1 R1-2 C4-2 C3-2 U1-15 CONN1-11 CONN1-10 CONN1-5 DTRD J30-2 CONN1-4
GND C31-2 R32-1 U30-2 C11-2 C12-2 C13-2 Q2-4 Q2-1 Q4-1 Q4-4 Q3-4 Q3-1 J1-6 D8-1 C7-1 C8-2 BOARD-1 R1-2 C4-2 C3-2 U1-15 CONN1-11 CONN1-10 CONN1-5

943
updi232.pcb
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69
updi232.sch
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@ -20,9 +20,9 @@ T 40200 47800 5 10 1 1 180 6 1
refdes=CONN1 refdes=CONN1
T 40200 47400 5 10 1 1 0 0 1 T 40200 47400 5 10 1 1 0 0 1
footprint=SUBD9_F footprint=SUBD9_F
T 39900 48300 5 10 1 1 90 0 1
value=D9 fem 90° backset 8.1mm
T 40200 47200 5 10 1 1 0 0 1 T 40200 47200 5 10 1 1 0 0 1
value=D9-Female-E-90°
T 40200 47000 5 10 1 1 0 0 1
net=GND:10,11 net=GND:10,11
} }
C 45300 47300 1 0 0 max232.sym C 45300 47300 1 0 0 max232.sym
@ -130,10 +130,12 @@ N 42600 47600 45300 47600 4
T 44800 47650 5 7 1 1 0 0 1 T 44800 47650 5 7 1 1 0 0 1
netname=TxDD netname=TxDD
} }
N 41700 48800 45300 48800 4 N 41200 48800 45300 48800 4
{ {
T 44800 48850 5 7 1 1 0 0 1 T 44800 48850 5 7 1 1 0 0 1
netname=RxDD netname=RxDD
T 41300 48850 5 5 1 1 0 0 1
netname=RxDD
} }
C 48900 49500 1 90 0 gnd-1.sym C 48900 49500 1 90 0 gnd-1.sym
C 41500 50500 1 90 0 gnd-1.sym C 41500 50500 1 90 0 gnd-1.sym
@ -155,12 +157,6 @@ device=none
T 47800 47600 5 10 1 1 0 4 1 T 47800 47600 5 10 1 1 0 4 1
value=TxD value=TxD
} }
N 41700 48800 41700 48500 4
N 41200 48500 41700 48500 4
{
T 41300 48550 5 5 1 1 0 0 1
netname=RxDD
}
C 47300 48300 1 0 0 io-1.sym C 47300 48300 1 0 0 io-1.sym
{ {
T 48200 48500 5 10 0 0 0 0 1 T 48200 48500 5 10 0 0 0 0 1
@ -512,7 +508,7 @@ refdes=J1
T 53700 44400 5 10 0 1 0 0 1 T 53700 44400 5 10 0 1 0 0 1
footprint=HE_100mil_6_2 footprint=HE_100mil_6_2
} }
C 40100 45100 1 0 0 gnd-1.sym C 40000 45100 1 0 0 gnd-1.sym
T 53050 46500 5 5 1 1 0 1 1 T 53050 46500 5 5 1 1 0 1 1
netname=SCK netname=SCK
T 53050 46100 5 5 1 1 0 1 1 T 53050 46100 5 5 1 1 0 1 1
@ -525,7 +521,7 @@ T 53750 46100 5 5 1 1 180 1 1
netname=GND netname=GND
T 53050 46900 5 5 1 1 0 1 1 T 53050 46900 5 5 1 1 0 1 1
netname=MISO netname=MISO
C 40000 46300 1 0 0 vcc-1.sym C 40500 46300 1 0 0 vcc-1.sym
C 52600 47000 1 180 0 io-1.sym C 52600 47000 1 180 0 io-1.sym
{ {
T 51700 46800 5 10 0 0 180 0 1 T 51700 46800 5 10 0 0 180 0 1
@ -891,6 +887,21 @@ footprint=P1206
T 41000 45900 5 10 0 1 90 4 1 T 41000 45900 5 10 0 1 90 4 1
value=10µF value=10µF
} }
C 39900 46300 1 270 0 capacitor-1.sym
{
T 40600 46100 5 10 0 0 270 0 1
device=CAPACITOR
T 40800 46100 5 10 0 0 270 0 1
symversion=0.2
T 40600 46100 5 10 0 1 270 0 1
footprint=C0603
T 40250 45750 5 10 0 1 90 6 1
value=100nF
T 40150 45750 5 10 1 1 180 6 1
refdes=C12
}
N 40100 45400 41300 45400 4
N 40700 46300 41300 46300 4
C 40500 46300 1 270 0 capacitor-1.sym C 40500 46300 1 270 0 capacitor-1.sym
{ {
T 41200 46100 5 10 0 0 270 0 1 T 41200 46100 5 10 0 0 270 0 1
@ -902,21 +913,6 @@ footprint=C0603
T 40850 45750 5 10 0 1 90 6 1 T 40850 45750 5 10 0 1 90 6 1
value=100nF value=100nF
T 40750 45750 5 10 1 1 180 6 1 T 40750 45750 5 10 1 1 180 6 1
refdes=C12
}
N 41300 45400 40200 45400 4
N 40200 46300 41300 46300 4
C 40000 46300 1 270 0 capacitor-1.sym
{
T 40700 46100 5 10 0 0 270 0 1
device=CAPACITOR
T 40900 46100 5 10 0 0 270 0 1
symversion=0.2
T 40700 46100 5 10 0 1 270 0 1
footprint=C0603
T 40350 45750 5 10 0 1 90 6 1
value=100nF
T 40250 45750 5 10 1 1 180 6 1
refdes=C11 refdes=C11
} }
C 54300 47400 1 270 0 vcc-1.sym C 54300 47400 1 270 0 vcc-1.sym
@ -993,7 +989,7 @@ C 55300 44000 1 90 0 resistor-2.sym
T 54950 44400 5 10 0 0 90 0 1 T 54950 44400 5 10 0 0 90 0 1
device=RESISTOR device=RESISTOR
T 54800 44200 5 10 0 1 90 0 1 T 54800 44200 5 10 0 1 90 0 1
footprint=C0603.fp footprint=C0603
T 54600 44200 5 10 0 0 90 0 1 T 54600 44200 5 10 0 0 90 0 1
symversion=0.1 symversion=0.1
T 55300 44450 5 10 1 1 90 5 1 T 55300 44450 5 10 1 1 90 5 1
@ -1012,7 +1008,7 @@ C 55300 43100 1 90 0 resistor-2.sym
T 54950 43500 5 10 0 0 90 0 1 T 54950 43500 5 10 0 0 90 0 1
device=RESISTOR device=RESISTOR
T 54800 43300 5 10 0 1 90 0 1 T 54800 43300 5 10 0 1 90 0 1
footprint=C0603.fp footprint=C0603
T 54600 43300 5 10 0 0 90 0 1 T 54600 43300 5 10 0 0 90 0 1
symversion=0.1 symversion=0.1
T 55300 43550 5 10 1 1 90 5 1 T 55300 43550 5 10 1 1 90 5 1
@ -1049,7 +1045,7 @@ device=CAPACITOR
T 51800 44700 5 10 0 0 0 0 1 T 51800 44700 5 10 0 0 0 0 1
symversion=0.2 symversion=0.2
T 51800 44500 5 10 0 1 0 0 1 T 51800 44500 5 10 0 1 0 0 1
footprint=C_0603 footprint=C0603
T 52100 44000 5 10 1 1 0 2 1 T 52100 44000 5 10 1 1 0 2 1
refdes=C30 refdes=C30
T 51600 43600 5 10 1 1 0 0 1 T 51600 43600 5 10 1 1 0 0 1
@ -1099,17 +1095,17 @@ C 41900 50200 1 0 0 resistor-2.sym
T 42300 50550 5 10 0 0 0 0 1 T 42300 50550 5 10 0 0 0 0 1
device=RESISTOR device=RESISTOR
T 42100 50700 5 10 0 1 0 0 1 T 42100 50700 5 10 0 1 0 0 1
footprint=C0603.fp footprint=C0603
T 42100 50900 5 10 0 0 0 0 1 T 42100 50900 5 10 0 0 0 0 1
symversion=0.1 symversion=0.1
T 42350 50200 5 10 1 1 0 5 1 T 42350 50200 5 10 1 1 0 5 1
refdes=R32 refdes=R33
T 42350 50450 5 10 1 1 0 3 1 T 42350 50450 5 10 1 1 0 3 1
value=100Ω value=100Ω
} }
N 41200 50000 41800 50000 4 N 41200 50000 41800 50000 4
{ {
T 41200 50050 5 7 1 1 0 0 1 T 41300 50050 5 5 1 1 0 0 1
netname=DTRD netname=DTRD
} }
N 42800 50300 43100 50300 4 N 42800 50300 43100 50300 4
@ -1142,7 +1138,7 @@ U30 will tollerate negative input voltage
and any voltage on the output without input voltage. and any voltage on the output without input voltage.
T 45700 41300 9 8 1 0 0 0 3 T 45700 41300 9 8 1 0 0 0 3
TxD and RxD need to be non-inverting. TxD and RxD need to be non-inverting.
CTS may be inverting ot non-inverting. RTS may be inverting ot non-inverting.
What is the default level on that pin? What is the default level on that pin?
T 41700 50900 9 8 1 0 0 0 3 T 41700 50900 9 8 1 0 0 0 3
DTR should be able to supply a few mA DTR should be able to supply a few mA
@ -1191,3 +1187,10 @@ N 41200 49400 42600 49400 4
T 41300 49450 5 5 1 1 0 0 1 T 41300 49450 5 5 1 1 0 0 1
netname=TxDD netname=TxDD
} }
C 39900 46300 1 0 0 generic-power.sym
{
T 40100 46550 5 10 0 1 0 3 1
net=VccT:1
T 40100 46550 5 7 1 1 0 3 1
description=VccT
}

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