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datalogger/dlrena/sym
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Stephan I. Böttcher e799df39e6 dlrena layout implements sch changes + 
sch → pcb
add a UART and Power connector for flashing w/o Mezz connection
2024-10-21 21:10:06 +02:00
..
fp dlrena: layout complete, drc, refdes 2024-10-19 23:01:14 +02:00
74LVC4T33144.sym dlrena: add 74LVC4T33144 symbol 2024-04-22 19:51:16 +02:00
AD8005-1.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
ADA4177-4-ssop14.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
ADS8688_TSSOP38.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
armgnd.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
AT45DB081D-1.sym dlrena: add missing subschematics 2024-04-25 19:19:17 +02:00
CONN64.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
current-sense.sch dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
current-sense.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
flash-1.sch dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
flash.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
header3.sym dlrena: connections and jumpers drawn in sch 2024-10-18 11:38:35 +02:00
header4.sym diff ain 2024-10-17 16:41:49 +02:00
header6.sym dlrena layout implements sch changes + 2024-10-21 21:10:06 +02:00
irasboard.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
LDO+1.sch dlrena: copy nmrena layout, fp, run lepton-sch2pcb 2024-04-23 21:24:22 +02:00
LDO-1.sch dlrena: copy nmrena layout, fp, run lepton-sch2pcb 2024-04-23 21:24:22 +02:00
LDO-1.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
LPC2148.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
LT1761ES5-BYP.sym dlrena: add missing subschematics 2024-04-25 19:19:17 +02:00
LT1964ES5-BYP.sym dlrena: add missing subschematics 2024-04-25 19:19:17 +02:00
LTC2656-TSSOP20.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
lvds-rx.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
lvds-tx.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
max232.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
microsd.sym dlrena: add missing subschematics 2024-04-25 19:19:17 +02:00
MS5534C.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
npn-sot23.sym dlrena layout implements sch changes + 2024-10-21 21:10:06 +02:00
OSCILLATOR.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
pwrgnd.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
RESET.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
resistor-kc.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00
resistors-4.sym dlrena: copy of nmrena w/o FPGA 2024-04-21 15:38:30 +02:00