Compare commits

...

15 commits

Author SHA1 Message Date
Stephan I. Böttcher
6cea8bb18e Merge branch 'master' of forge.bexus.org:Stephan/irena-arm 2025-03-03 21:21:06 +01:00
Stephan I. Böttcher
cbe5764824 i2c/run: fix i2c_size bookkeeping 2025-03-03 21:20:40 +01:00
Stephan I. Böttcher
6f3533ac03 i2c: accept /mag,/acc without additional argument 2025-03-03 21:20:40 +01:00
Stephan I. Böttcher
cd0861a6ca altera_set_register: allow preset writes of zero 2025-03-03 21:20:40 +01:00
Stephan I. Böttcher
7d206539bd i2c/addr: optional_expression 2025-03-03 21:20:40 +01:00
Stephan I. Böttcher
029b541db5 parse_expression_square: fix optional_brackets 2025-03-03 21:20:40 +01:00
Stephan I. Böttcher
5f3e2d4891 dorn_l*: how parameter 2025-03-03 20:19:18 +00:00
Stephan I. Böttcher
ab532e2c2b altera_set_reg: remove unnecessary condition 2025-03-03 20:19:18 +00:00
Stephan I. Böttcher
8c11bb2f21 dorn: force write to mem registers 2025-03-03 20:19:18 +00:00
Stephan I. Böttcher
f3fe0119e9 parse_index: initialize a 2025-03-03 20:19:18 +00:00
stephan
008c65b4db nmahepam: bitfile w I²C, bate, nmcounter
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda/arm@9309 bc5caf13-1734-44f8-af43-603852e9ee25
2025-03-03 20:14:39 +00:00
stephan
79bee7b432 nmahepam: enable all slices
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda/arm@9308 bc5caf13-1734-44f8-af43-603852e9ee25
2025-03-03 20:12:45 +00:00
stephan
5d674c2041 nmahepam CRON: 12s cadence w/ pressure
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda/arm@9302 bc5caf13-1734-44f8-af43-603852e9ee25
2025-03-03 09:35:52 +00:00
stephan
046ffbba58 arm: add module plltest
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda/arm@9300 bc5caf13-1734-44f8-af43-603852e9ee25
2025-03-02 21:40:28 +00:00
stephan
05e61e8bb3 nmahepam: AHBOG()
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda/arm@9292 bc5caf13-1734-44f8-af43-603852e9ee25
2025-03-02 09:42:11 +00:00
4 changed files with 61 additions and 6 deletions

View file

@ -1,6 +1,8 @@
@clock/short
@s/if sec & 1 and I: al/cmd/inj I; s/exit
@s/if sec==0: nm/cou/re/cl/fl; s/exit
@s/if sec==2 and H: al/cmd/inj H
@s/if sec==4: v hk_c=1; s/exit
@s/if sec==6 and hk_mes>1: v hk_c=hk_mes-1; s/exit
@v S=sec%12
@s/if hk_mes>1: v hk_c=1
@s/if !S: nm/cou/re/cl/fl; s/exit
@s/if S&1 and I: al/cmd/inj I; s/exit
@s/if S&2: pres/inj; s/exit
@s/if S&4: v hk_c=1; s/exit
@s/if S&8 and H: al/cmd/inj H; s/exit

Binary file not shown.

View file

@ -93,7 +93,23 @@ def hk(sl, what="print", data=None):
sys.stderr.write(r)
return r
def aenable(sl=1, hk=True, ev=True, **aa):
def TBITS(t):
return sum([1<<n for n in t])
def AHBGO():
global BGO, UNTEN, OBEN, SSD
BGO = 6,7,13,15,22,23
UNTEN = 2,3,4,11,12,19,20,21
OBEN = 0,1,8,9,10,16,17,18
# ch 18 has a problem?
OBEN = 0,1,8,9,10,16,17
SSD = OBEN + UNTEN
default_config()
atriggers(1, TBITS(BGO))
for c in SSD: thres(1, c, 8)
for c in BGO: thres(1, c, 8)
def aenable(sl=None, hk=True, ev=True, **aa):
cmd("s/cron 'CRON.RC'")
fifo_enable(sl=sl, hk=hk, ev=ev, **aa)
enable()

37
plltest.py Normal file
View file

@ -0,0 +1,37 @@
def wavestr(b, n=16, lr=("__", "/ ", "\\_", " ")):
bb = [ (b >> (n-2-i)) & 3 for i in range(n-1) ]
return "".join([lr[bbb] for bbb in bb])
class plltest:
def __init__(self, ifc=None):
if ifc:
self._connect(ifc)
self.read()
def _connect(self, ifc):
if isinstance(ifc, list):
self.default = ifc
self.Areg = lambda i: self.default[i&3]
return
try:
self.Areg = ifc.Areg
except:
self.Areg = ifc
base_addr = 0x400
names = ["96MHz", "64MHz", "32MHz", "16MHz"]
def read(self):
n = len(self.names)
self.bits = list(map(self.Areg, range(self.base_addr, self.base_addr+n)))
def __repr__(self):
r = []
for i,b in enumerate(self.bits):
nn = self.names[i]
r.append(f"{'':8.8s} {wavestr(b, 16, (" ", " _", " ", "__"))}")
r.append(f"{nn:8.8s} {wavestr(b, 16, ("__", "/ ", "\\_", " "))}")
return "\n".join(r)