This program implements ARM7 firmware for the IRENA family of data
acquisition instruments that are develeoped and used at the Institute
for Experimantal and Applied Physics at the Christian-Albrechts-
University in Kiel, Germany.

Copyright (c) 2010-2011 Christian-Albrechts-Universität zu Kiel
Copyright (c) 2010-2011 Stephan Böttcher

This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or (at
your option) any later version.

This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.

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From here on you can read early concepts, which may have been
implemented as outlined, or differently, please refer to the code.

Fosc: 12 MHz
CCLK: 60 MHz
PCLK: 60 MHz
USBCLK: 48 MHz

Peripherals:
  
   USB
      control pipe for commands, 
         handled by ISR, feeding command queue.
         returns command status

      bulk OUT for command payloads.
         handled by DMA and ISR
         consumed by command queue, FPGA config. 

      bulk IN for fifo streaming or command returns. 
         handled by DMA and ISR
         fed by FPGA or SD card

    SPI
       7.5 Mbps steaming in tight busy-wait loop
       sd-card without filesystem, sequential block reads.
       flash with R/O FAT16 filesystem.

    SSP
       25 Mbps in tight busy-wait loop
       streaming FPGA output into DMA RAM

    UART0
       handled by ISR
       feeding command queue

    ADCs
       houskeeping reads

    TIMER1 supplies a clock to the FPGA
    TIMER0 captures attn from the FPGA

    RTC 
       provides time since power on.


    GPIO0
       SSel for SPI (3 outputs)

    GPIO1
       FPGA configuration.  Software serial (with SSP polling?)


Nothing ever blocks except in a tight loop serving the SPI and SSP
streams.  SPI synchronous IO with SSP polling in the innermost poll
loop.  FPGA config with SSP polling.

No jiffies.

SSP stream modes:
   idle:   no SPI activity.
   write:  send a buffer, capture without 0EFF_0EFF filter.
   read:   read response, capture without 0EFF_0EFF filter, send NOPs
   fifo:   send FIFO_read, capture with 0EFF_0EFF compression filter
All data goes into DMA RAM.

Commands:

  Read flash to USB
  Write flash from USB
  Erase flash block?

  Read SD to USB
  Write SD from USB
  Erase SD-card?
  
  Write FPGA register (SSP)
  Read FPGA response (last n words from DMA RAM ring buffer)

  Set FPGA fifo streaming mode (SD and/or USB)
  
  Boot FPGA from flash file
  Boot FPGA from USB

  Write RAM from flash file
  Write RAM from USB
  Read memory to USB.
  Execute command script.
  Goto address.
  

DMA RAM:  
   4kByte Ring Buffer for FPGA output
   Command payload IN OUT buffers.
   DDs.

Main RAM: 
   code, 
   command scripts.
   status

Boot: 
   Initialize Hardware, SD-card.
   If USB present, or UART activity:
      enter main command loop, wait for USB/UART commands
   Else
      read file INIT and execute script
   Else
      read file IMAGE and goto RAM reset vector