Stephan/irena-avr
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1 changed files with 32 additions and 34 deletions
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64
leia/leia.c
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@ -96,12 +96,10 @@ struct vars {
struct stat stat; struct stat stat;
} v; } v;
#define CPUCLK 11059200L #define STEP_RESOLUTION 23148L // ns
#define STEP_RESOLUTION (256000000000LL/CPUCLK) #define STEP_NS(ns) (((ns)+STEP_RESOLUTION/2)/STEP_RESOLUTION)
#define TICK_RESOLUTION (1024000000000LL/CPUCLK) #define TICK_RESOLUTION 92593L // ns
#define NS(ns,res) (((ns)+(res)/2)/(res)) #define TICK_NS(ns) (((ns)+TICK_RESOLUTION/2)/TICK_RESOLUTION)
#define STEP_NS(ns) NS(ns, STEP_RESOLUTION)
#define TICK_NS(ns) NS(ns, TICK_RESOLUTION)
#define ADC_E (1<<REFS0) #define ADC_E (1<<REFS0)
#define ADC_S (ADC_E | 1<<ADLAR) #define ADC_S (ADC_E | 1<<ADLAR)
@ -134,11 +132,12 @@ const struct conf runcon = {
// The DAC uses the Vref selected here. For proper operation, // The DAC uses the Vref selected here. For proper operation,
// all entries must use the same Vref! // all entries must use the same Vref!
.adc_ch = { .adc_ch = {
ADC_Vcc|DAC_S, ADC_Vcc|DAC_R,
ADC_BG|DAC_S, ADC_BG|DAC_R, ADC_BG|DAC_S, ADC_BG|DAC_R,
ADC_GND|DAC_S, ADC_GND|DAC_R, ADC_GND|DAC_S, ADC_GND|DAC_R,
ADC_Iprim|DAC_S, ADC_Iprim|DAC_R, ADC_Iprim|DAC_S, ADC_Iprim|DAC_R,
ADC_Vcc|DAC_S, ADC_Vcc|DAC_R,
ADC_Temp|DAC_R, ADC_Temp|DAC_R,
ADC_Iprim|DAC_R,
ADC_NTC1|DAC_R, ADC_NTC2|DAC_R, ADC_NTC3|DAC_R, ADC_NTC1|DAC_R, ADC_NTC2|DAC_R, ADC_NTC3|DAC_R,
}, },
.dac_ref = DAC_R | ADC_BG, .dac_ref = DAC_R | ADC_BG,
@ -434,7 +433,7 @@ void adc_stop()
ADCSRA = 1<<ADEN | 1<<ADIF | 6<<ADPS0; ADCSRA = 1<<ADEN | 1<<ADIF | 6<<ADPS0;
} }
#if 0 #if 1
ISR(ADC_vect) ISR(ADC_vect)
{ {
uint16_t a; uint16_t a;
@ -472,7 +471,7 @@ ISR(ADC_vect, ISR_NAKED)
"push r30" "\n\t" "push r30" "\n\t"
"push r31" "\n\t" "push r31" "\n\t"
"lds r24, %[X]" "\n\t" "lds r24, %[X]" "\n\t"
"sbrs r24, %[XA]" "\n\t" "sbrs r24, %[XL]" "\n\t"
"rjmp 5f" "\n\t" "rjmp 5f" "\n\t"
"ldi r30, 0x1f" "\n\t" "ldi r30, 0x1f" "\n\t"
"and r30, r24" "\n\t" "and r30, r24" "\n\t"
@ -487,20 +486,20 @@ ISR(ADC_vect, ISR_NAKED)
"andi r30, 0x0f" "\n\t" "andi r30, 0x0f" "\n\t"
"lsl r30" "\n\t" "lsl r30" "\n\t"
"ldi r31, 0" "\n\t" "ldi r31, 0" "\n\t"
"subi r30, lo8(-(%[D]))" "\n\t" "subi r30, lo8(%[D])" "\n\t"
"sbci r31, hi8(-(%[D]))" "\n\t" "sbci r31, hi8(%[D])" "\n\t"
"st Z, r24" "\n\t" "st Z, r24" "\n\t"
"lds r24, %[AH]" "\n\t" "lds r24, %[AH]" "\n\t"
"std Z+1, r24" "\n\t" "std Z+1, r24" "\n\t"
"rjmp 6f" "\n" "jjmp 6f" "\n"
"5:" "\n\t" "5:" "\n\t"
"lds r30, %[I]" "\n\t" "lds r30, %[I]" "\n\t"
"swap r30" "\n\t" "swap r30" "\n\t"
"andi r30, 0x0f" "\n\t" "andi r30, 0x0f" "\n\t"
"lsl r30" "\n\t" "lsl r30" "\n\t"
"ldi r31, 0" "\n\t" "ldi r31, 0" "\n\t"
"subi r30, lo8(-(%[D]))" "\n\t" "subi r30, lo8(%[D])" "\n\t"
"sbci r31, hi8(-(%[D]))" "\n\t" "sbci r31, hi8(%[D])" "\n\t"
"push r22" "\n\t" "push r22" "\n\t"
"push r25" "\n\t" "push r25" "\n\t"
"ld r24, Z" "\n\t" "ld r24, Z" "\n\t"
@ -520,23 +519,31 @@ ISR(ADC_vect, ISR_NAKED)
"add r24, r22" "\n\t" "add r24, r22" "\n\t"
"st Z, r24" "\n\t" "st Z, r24" "\n\t"
"lds r22, %[AH]" "\n\t" "lds r22, %[AH]" "\n\t"
"adc r25, r22" "\n\t" "adc r24, r22" "\n\t"
"std Z+1, r25" "\n\t" "std Z+1, r24" "\n\t"
"pop r25" "\n\t" "pop r25" "\n\t"
"pop r22" "\n" "pop r22" "\n"
"6:" "\n\t" "6:" "\n\t"
"lds r24, %[I]" "\n\t" "lds r24, %[I]" "\n\t"
"lds r30, %[II]" "\n\t" "lds r30, %[II]" "\n\t"
"add r30, r24" "\n\t" "add r30, r24" "\n\t"
"sts %[I], r30" "\n\t" "sts %[II], r30" "\n\t"
"swap r30" "\n\t" "swap r30" "\n\t"
"andi r30, 0x0f" "\n\t" "andi r30, 0x0f" "\n\t"
"ldi r31, 0" "\n\t" "ldi r31, 0" "\n\t"
"subi r30, lo8(-(%[C]))" "\n\t" "subi r30, lo8(%[C])" "\n\t"
"sbci r31, hi8(-(%[C]))" "\n\t" "sbci r31, hi8(%[C])" "\n\t"
"ld r24, Z" "\n\t" "ld r24, Z" "\n\t"
"sbrs r24, %[XR]" "\n\t" "sbrc r24, %[XR]" "\n\t"
"rjmp 7f" "\n\t" "rjmp 1f" "\n\t"
"clr r24" "\n\t"
"sts %[II], r24" "\n\t"
"lds r24, %[C]" "\n\t"
"sbrc r24, %[XR]" "\n\t"
"rjmp 1f" "\n\t"
"ldi r24, %[AA]" "\n\t"
"sts %[A], r24" "\n\t"
"rjmp 2f" "\n"
"1:" "\n\t" "1:" "\n\t"
"sts %[X], r24" "\n\t" "sts %[X], r24" "\n\t"
"sbi %[F], %[FF]" "\n" "sbi %[F], %[FF]" "\n"
@ -547,15 +554,6 @@ ISR(ADC_vect, ISR_NAKED)
"out __SREG__, r24" "\n\t" "out __SREG__, r24" "\n\t"
"pop r24" "\n\t" "pop r24" "\n\t"
"reti" "\n" "reti" "\n"
"7:" "\n\t"
"clr r24" "\n\t"
"sts %[I], r24" "\n\t"
"lds r24, %[C]" "\n\t"
"sbrc r24, %[XR]" "\n\t"
"rjmp 1b" "\n\t"
"ldi r24, %[AA]" "\n\t"
"sts %[A], r24" "\n\t"
"rjmp 2b" "\n"
:[I] "+m" (v.stat.adc_idx), :[I] "+m" (v.stat.adc_idx),
[D] "+m" (v.stat.adc) [D] "+m" (v.stat.adc)
:[C] "m" (v.conf.adc_ch), :[C] "m" (v.conf.adc_ch),
@ -564,11 +562,11 @@ ISR(ADC_vect, ISR_NAKED)
[AH] "n" (_SFR_MEM_ADDR(ADCH)), [AH] "n" (_SFR_MEM_ADDR(ADCH)),
[X] "n" (_SFR_MEM_ADDR(ADMUX)), [X] "n" (_SFR_MEM_ADDR(ADMUX)),
[XR] "n" (REFS0), [XR] "n" (REFS0),
[XA] "n" (ADLAR), [XL] "n" (ADLAR),
[A] "n" (_SFR_MEM_ADDR(ADCSRA)), [A] "n" (_SFR_MEM_ADDR(ADCSRA)),
[AA] "n" (1<<ADEN | 1<<ADIF | 6<<ADPS0), [AA] "n" (1<<ADEN | 1<<ADIF | 6<<ADPS0),
[F] "n" (_SFR_IO_ADDR(TIFR0)), [F] "n" (_SFR_IO_ADDR(TIFR0)),
[FF] "n" (OCF0B) [FF] "n" (OCF10B)
); );
} }
#endif #endif
@ -633,7 +631,7 @@ ISR(EE_READY_vect, ISR_NAKED)
"out %[AH], r30" "\n\t" "out %[AH], r30" "\n\t"
"sbi %[C], %[RE]" "\n\t" "sbi %[C], %[RE]" "\n\t"
"ldi r30, lo8(%[V])" "\n\t" "ldi r30, lo8(%[V])" "\n\t"
"ldi r31, hi8(%[V])" "\n\t" "ldi r31, hi8($[V])" "\n\t"
"add r30, r24" "\n\t" "add r30, r24" "\n\t"
"brcc 3f" "\n\t" "brcc 3f" "\n\t"
"subi r31, -1" "\n" "subi r31, -1" "\n"