Stephan/irena-avr
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base: Stephan:100f07b9f5b610e485977c5370b3a848e784b77d
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compare: Stephan:04e72a30109f91470034da3ed6774ebe4209e521
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3 commits
100f07b9f5 ... 04e72a3010

Author SHA1 Message Date
Stephan I. Böttcher
04e72a3010 leia: fix adc isr 
- XL is a macro from avr/io.h, avoid as asm param
- SUBI the negative memory location, 3×
- s/jjmp/rjmp/
- store the high byte of avg
- store the index into the correct location s/II/I/, 2×
- optimize for the likely code path
- s/OCF10B/OCF0B/

eeprom isr: (not yet enabled/tested)

- s/$[V]/%[V]/
 2025-10-29 15:32:39 +01:00
Stephan I. Böttcher
f0f9b8acab leia: convert VCC first, as reference for NTCs 2025-10-29 12:15:11 +01:00
Stephan I. Böttcher
530fedca69 leia: TICK by CPUCLK 2025-10-29 10:54:00 +01:00
1 changed files with 34 additions and 32 deletions
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66
leia/leia.c
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@ -96,10 +96,12 @@ struct vars {
struct stat stat;
} v;
#define STEP_RESOLUTION 23148L // ns
#define STEP_NS(ns) (((ns)+STEP_RESOLUTION/2)/STEP_RESOLUTION)
#define TICK_RESOLUTION 92593L // ns
#define TICK_NS(ns) (((ns)+TICK_RESOLUTION/2)/TICK_RESOLUTION)
#define CPUCLK 11059200L
#define STEP_RESOLUTION (256000000000LL/CPUCLK)
#define TICK_RESOLUTION (1024000000000LL/CPUCLK)
#define NS(ns,res) (((ns)+(res)/2)/(res))
#define STEP_NS(ns) NS(ns, STEP_RESOLUTION)
#define TICK_NS(ns) NS(ns, TICK_RESOLUTION)
#define ADC_E (1<<REFS0)
#define ADC_S (ADC_E | 1<<ADLAR)
@ -132,12 +134,11 @@ const struct conf runcon = {
// The DAC uses the Vref selected here. For proper operation,
// all entries must use the same Vref!
.adc_ch = {
ADC_BG|DAC_S, ADC_BG|DAC_R,
ADC_Vcc|DAC_S, ADC_Vcc|DAC_R,
ADC_BG |DAC_S, ADC_BG |DAC_R,
ADC_GND|DAC_S, ADC_GND|DAC_R,
ADC_Iprim|DAC_S, ADC_Iprim|DAC_R,
ADC_Vcc|DAC_S, ADC_Vcc|DAC_R,
ADC_Temp|DAC_R,
ADC_Iprim|DAC_R,
ADC_NTC1|DAC_R, ADC_NTC2|DAC_R, ADC_NTC3|DAC_R,
},
.dac_ref = DAC_R | ADC_BG,
@ -433,7 +434,7 @@ void adc_stop()
ADCSRA = 1<<ADEN | 1<<ADIF | 6<<ADPS0;
}
#if 1
#if 0
ISR(ADC_vect)
{
uint16_t a;
@ -471,7 +472,7 @@ ISR(ADC_vect, ISR_NAKED)
"push r30" "\n\t"
"push r31" "\n\t"
"lds r24, %[X]" "\n\t"
"sbrs r24, %[XL]" "\n\t"
"sbrs r24, %[XA]" "\n\t"
"rjmp 5f" "\n\t"
"ldi r30, 0x1f" "\n\t"
"and r30, r24" "\n\t"
@ -486,20 +487,20 @@ ISR(ADC_vect, ISR_NAKED)
"andi r30, 0x0f" "\n\t"
"lsl r30" "\n\t"
"ldi r31, 0" "\n\t"
"subi r30, lo8(%[D])" "\n\t"
"sbci r31, hi8(%[D])" "\n\t"
"subi r30, lo8(-(%[D]))" "\n\t"
"sbci r31, hi8(-(%[D]))" "\n\t"
"st Z, r24" "\n\t"
"lds r24, %[AH]" "\n\t"
"std Z+1, r24" "\n\t"
"jjmp 6f" "\n"
"rjmp 6f" "\n"
"5:" "\n\t"
"lds r30, %[I]" "\n\t"
"swap r30" "\n\t"
"andi r30, 0x0f" "\n\t"
"lsl r30" "\n\t"
"ldi r31, 0" "\n\t"
"subi r30, lo8(%[D])" "\n\t"
"sbci r31, hi8(%[D])" "\n\t"
"subi r30, lo8(-(%[D]))" "\n\t"
"sbci r31, hi8(-(%[D]))" "\n\t"
"push r22" "\n\t"
"push r25" "\n\t"
"ld r24, Z" "\n\t"
@ -519,31 +520,23 @@ ISR(ADC_vect, ISR_NAKED)
"add r24, r22" "\n\t"
"st Z, r24" "\n\t"
"lds r22, %[AH]" "\n\t"
"adc r24, r22" "\n\t"
"std Z+1, r24" "\n\t"
"adc r25, r22" "\n\t"
"std Z+1, r25" "\n\t"
"pop r25" "\n\t"
"pop r22" "\n"
"6:" "\n\t"
"lds r24, %[I]" "\n\t"
"lds r30, %[II]" "\n\t"
"add r30, r24" "\n\t"
"sts %[II], r30" "\n\t"
"sts %[I], r30" "\n\t"
"swap r30" "\n\t"
"andi r30, 0x0f" "\n\t"
"ldi r31, 0" "\n\t"
"subi r30, lo8(%[C])" "\n\t"
"sbci r31, hi8(%[C])" "\n\t"
"subi r30, lo8(-(%[C]))" "\n\t"
"sbci r31, hi8(-(%[C]))" "\n\t"
"ld r24, Z" "\n\t"
"sbrc r24, %[XR]" "\n\t"
"rjmp 1f" "\n\t"
"clr r24" "\n\t"
"sts %[II], r24" "\n\t"
"lds r24, %[C]" "\n\t"
"sbrc r24, %[XR]" "\n\t"
"rjmp 1f" "\n\t"
"ldi r24, %[AA]" "\n\t"
"sts %[A], r24" "\n\t"
"rjmp 2f" "\n"
"sbrs r24, %[XR]" "\n\t"
"rjmp 7f" "\n\t"
"1:" "\n\t"
"sts %[X], r24" "\n\t"
"sbi %[F], %[FF]" "\n"
@ -554,6 +547,15 @@ ISR(ADC_vect, ISR_NAKED)
"out __SREG__, r24" "\n\t"
"pop r24" "\n\t"
"reti" "\n"
"7:" "\n\t"
"clr r24" "\n\t"
"sts %[I], r24" "\n\t"
"lds r24, %[C]" "\n\t"
"sbrc r24, %[XR]" "\n\t"
"rjmp 1b" "\n\t"
"ldi r24, %[AA]" "\n\t"
"sts %[A], r24" "\n\t"
"rjmp 2b" "\n"
:[I] "+m" (v.stat.adc_idx),
[D] "+m" (v.stat.adc)
:[C] "m" (v.conf.adc_ch),
@ -562,11 +564,11 @@ ISR(ADC_vect, ISR_NAKED)
[AH] "n" (_SFR_MEM_ADDR(ADCH)),
[X] "n" (_SFR_MEM_ADDR(ADMUX)),
[XR] "n" (REFS0),
[XL] "n" (ADLAR),
[XA] "n" (ADLAR),
[A] "n" (_SFR_MEM_ADDR(ADCSRA)),
[AA] "n" (1<<ADEN | 1<<ADIF | 6<<ADPS0),
[F] "n" (_SFR_IO_ADDR(TIFR0)),
[FF] "n" (OCF10B)
[FF] "n" (OCF0B)
);
}
#endif
@ -631,7 +633,7 @@ ISR(EE_READY_vect, ISR_NAKED)
"out %[AH], r30" "\n\t"
"sbi %[C], %[RE]" "\n\t"
"ldi r30, lo8(%[V])" "\n\t"
"ldi r31, hi8($[V])" "\n\t"
"ldi r31, hi8(%[V])" "\n\t"
"add r30, r24" "\n\t"
"brcc 3f" "\n\t"
"subi r31, -1" "\n"