adctest.asm.rpt:Info: Quartus II Assembler was successful. 0 errors, 0 warnings
adctest.fit.rpt: 5. I/O Assignment Warnings
adctest.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
adctest.fit.rpt:; I/O Assignment Warnings ;
adctest.fit.rpt:Warning: Implemented PLL "pll240d_96:pll1|altpll:altpll_component|altpll_5v13:auto_generated|pll1" as Cyclone III PLL type, but with warnings
adctest.fit.rpt: Warning: Can't achieve requested value 69.1 degrees for clock output pll240d_96:pll1|altpll:altpll_component|altpll_5v13:auto_generated|clk[4] of parameter phase shift -- achieved value of 67.5 degrees
adctest.fit.rpt:Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
adctest.fit.rpt:Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
adctest.fit.rpt:Warning: Following 3 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
adctest.fit.rpt: Warning: Pin "LRx" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRx(n)"
adctest.fit.rpt: Warning: Pin "STx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "STx[1](n)"
adctest.fit.rpt: Warning: Pin "STx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "STx[2](n)"
adctest.fit.rpt:Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
adctest.fit.rpt:Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
adctest.fit.rpt:Warning: 9 pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems).
adctest.fit.rpt:Info: Quartus II Fitter was successful. 0 errors, 11 warnings
adctest.map.rpt:; rrn ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (7 bits) it drives. The 25 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
adctest.map.rpt:; dout1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
adctest.map.rpt:; doute ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
adctest.map.rpt:; din1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
adctest.map.rpt:; dine ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
adctest.map.rpt:Warning: Output pins are stuck at VCC or GND
adctest.map.rpt: Warning (13410): Pin "LTxp" is stuck at GND
adctest.map.rpt: Warning (13410): Pin "LTxn" is stuck at GND
adctest.map.rpt: Warning (13410): Pin "SDATAIN" is stuck at GND
adctest.map.rpt:Warning: PLL "pll240d_96:pll1|altpll:altpll_component|altpll_5v13:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
adctest.map.rpt:Warning: PLL "pll240d_96:pll1|altpll:altpll_component|altpll_5v13:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
