quartus/ahepam_ana_demo_c10.asm.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
quartus/ahepam_ana_demo_c10.asm.rpt:Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
quartus/ahepam_ana_demo_c10.fit.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
quartus/ahepam_ana_demo_c10.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
quartus/ahepam_ana_demo_c10.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
quartus/ahepam_ana_demo_c10.fit.rpt:Warning (176674): Following 6 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
quartus/ahepam_ana_demo_c10.fit.rpt: Warning (176118): Pin "ARxC" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARxC(n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_demo.v Line: 10
quartus/ahepam_ana_demo_c10.fit.rpt: Warning (176118): Pin "ARxD" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARxD(n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_demo.v Line: 10
quartus/ahepam_ana_demo_c10.fit.rpt: Warning (176118): Pin "L_IN[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "L_IN[1](n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_demo.v Line: 22
quartus/ahepam_ana_demo_c10.fit.rpt: Warning (176118): Pin "L_IN[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "L_IN[2](n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_demo.v Line: 22
quartus/ahepam_ana_demo_c10.fit.rpt: Warning (176118): Pin "L_IN[3]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "L_IN[3](n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_demo.v Line: 22
quartus/ahepam_ana_demo_c10.fit.rpt: Warning (176118): Pin "L_IN[4]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "L_IN[4](n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_demo.v Line: 22
quartus/ahepam_ana_demo_c10.fit.rpt:Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/ahepam_ana_demo_c10.fit.rpt:Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/ahepam_ana_demo_c10.fit.rpt:Warning (169177): 27 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone 10 LP Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
quartus/ahepam_ana_demo_c10.fit.rpt:Warning (169064): Following 22 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
quartus/ahepam_ana_demo_c10.fit.rpt:Info: Quartus Prime Fitter was successful. 0 errors, 14 warnings
quartus/ahepam_ana_demo_c10.map.rpt:; psize ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (16 bits) it drives. The 16 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
quartus/ahepam_ana_demo_c10.map.rpt:; psize ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (16 bits) it drives. The 16 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
quartus/ahepam_ana_demo_c10.map.rpt:; psize ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (16 bits) it drives. The 16 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
quartus/ahepam_ana_demo_c10.map.rpt:; RXn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/ahepam_ana_demo_c10.map.rpt:; fifof ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/ahepam_ana_demo_c10.map.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(45): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 45
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(51): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 51
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(52): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 52
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(67): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 67
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(68): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 68
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(69): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 69
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(70): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 70
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(287): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 287
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(288): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 288
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(289): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 289
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(290): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 290
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(291): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 291
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(293): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 293
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(294): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 294
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(296): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 296
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(297): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 297
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(298): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 298
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(299): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 299
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(301): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 301
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(302): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 302
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(304): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 304
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(449): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 449
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(450): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 450
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(451): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 451
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(452): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 452
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(594): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 594
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(689): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 689
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(690): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 690
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(691): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 691
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(692): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 692
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(693): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 693
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(694): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 694
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(695): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 695
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(696): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 696
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(697): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 697
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(698): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 698
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at multiply.v(10): Parameter Declaration in module "dorn_multiply" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/multiply.v Line: 10
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(971): Parameter Declaration in module "dorn_l3" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 971
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(972): Parameter Declaration in module "dorn_l3" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 972
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(973): Parameter Declaration in module "dorn_l3" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 973
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at divider.v(20): Parameter Declaration in module "dorn_divide" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 20
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(112): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 112
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(131): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 131
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(132): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 132
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(133): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 133
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(271): Parameter Declaration in module "dorn_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 271
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(272): Parameter Declaration in module "dorn_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 272
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(273): Parameter Declaration in module "dorn_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 273
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(274): Parameter Declaration in module "dorn_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 274
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(275): Parameter Declaration in module "dorn_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 275
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(276): Parameter Declaration in module "dorn_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 276
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(1092): Parameter Declaration in module "dorn_l4" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1092
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(1093): Parameter Declaration in module "dorn_l4" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1093
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(1094): Parameter Declaration in module "dorn_l4" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1094
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(1095): Parameter Declaration in module "dorn_l4" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1095
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10034): Output port "A" at ahepam_ana_demo.v(29) has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_demo.v Line: 29
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at ahepam_ana_core.v(170): truncated value with size 32 to match size of target (12) File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 170
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at ahepam_ana_core.v(190): truncated value with size 32 to match size of target (11) File: /home/blaulicht/stephan/svn@asterix/solo/eda/ahepam/altera/ahepam_ana_core.v Line: 190
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(359): truncated value with size 32 to match size of target (8) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 359
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(377): truncated value with size 32 to match size of target (8) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 377
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10036): Verilog HDL or VHDL warning at dorn.v(472): object "adc_valid" assigned a value but never read File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 472
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(500): truncated value with size 32 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 500
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(505): truncated value with size 4 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 505
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(532): truncated value with size 32 to match size of target (5) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 532
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(538): truncated value with size 32 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 538
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(545): truncated value with size 9 to match size of target (8) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 545
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(550): truncated value with size 10 to match size of target (9) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 550
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(562): truncated value with size 32 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 562
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(613): truncated value with size 13 to match size of target (12) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 613
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(75): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 75
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(163): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 163
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(759): truncated value with size 32 to match size of target (13) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 759
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(768): truncated value with size 32 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 768
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(775): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 775
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(797): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 797
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(801): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 801
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(828): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 828
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(834): truncated value with size 32 to match size of target (2) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 834
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(836): truncated value with size 32 to match size of target (2) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 836
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(848): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 848
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(850): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 850
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(872): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 872
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(882): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 882
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(883): truncated value with size 32 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 883
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(910): truncated value with size 32 to match size of target (26) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 910
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(1020): truncated value with size 32 to match size of target (2) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1020
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(1034): truncated value with size 32 to match size of target (2) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1034
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(38): truncated value with size 26 to match size of target (25) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 38
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(39): truncated value with size 26 to match size of target (25) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 39
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(40): truncated value with size 32 to match size of target (15) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 40
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(55): truncated value with size 26 to match size of target (25) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 55
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(57): truncated value with size 26 to match size of target (25) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 57
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(83): truncated value with size 32 to match size of target (15) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 83
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(85): truncated value with size 16 to match size of target (15) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 85
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(86): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 86
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(91): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 91
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/packetfifo.v Line: 70
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(151): truncated value with size 32 to match size of target (10) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/packetfifo.v Line: 151
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(172): truncated value with size 32 to match size of target (10) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/packetfifo.v Line: 172
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (5) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/countbits.v Line: 13
quartus/ahepam_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (10) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/countbits.v Line: 13
quartus/ahepam_ana_demo_c10.map.rpt:Warning (12241): 4 hierarchies have connectivity warnings - see the Connectivity Checks report folder
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(1306): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1306
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(538): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 538
quartus/ahepam_ana_demo_c10.sta.rpt: Warning (332030): Argument <to_clock> is not an object ID
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(538): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 538
quartus/ahepam_ana_demo_c10.sta.rpt: Warning (332030): Argument <to_clock> is not an object ID
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(538): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 538
quartus/ahepam_ana_demo_c10.sta.rpt: Warning (332030): Argument <to_clock> is not an object ID
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(538): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 538
quartus/ahepam_ana_demo_c10.sta.rpt: Warning (332030): Argument <to_clock> is not an object ID
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(973): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 973
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(538): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 538
quartus/ahepam_ana_demo_c10.sta.rpt: Warning (332030): Argument <to_clock> is not an object ID
quartus/ahepam_ana_demo_c10.sta.rpt:Warning (332174): Ignored filter at qsta_default_script.tcl(538): mclk could not be matched with a clock File: /usr/local/quartus/intelFPGA_lite/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 538
