quartus/harena.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/harena.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
quartus/harena.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
quartus/harena.fit.rpt:Warning (176674): Following 10 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
quartus/harena.fit.rpt: Warning (176118): Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
quartus/harena.fit.rpt: Warning (176118): Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
quartus/harena.fit.rpt: Warning (176118): Pin "adc_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "adc_clk(n)"
quartus/harena.fit.rpt: Warning (176118): Pin "ARx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[1](n)"
quartus/harena.fit.rpt: Warning (176118): Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
quartus/harena.fit.rpt: Warning (176118): Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
quartus/harena.fit.rpt: Warning (176118): Pin "ARx[3]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[3](n)"
quartus/harena.fit.rpt: Warning (176118): Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
quartus/harena.fit.rpt: Warning (176118): Pin "ARx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[2](n)"
quartus/harena.fit.rpt: Warning (176118): Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
quartus/harena.fit.rpt:Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/harena.fit.rpt:Warning (15064): PLL "pll96:pll0|altpll:altpll_component|altpll_lm43:auto_generated|pll1" output port clk[3] feeds output pin "ATxn[1]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
quartus/harena.fit.rpt:Warning (15064): PLL "pll96:pll0|altpll:altpll_component|altpll_lm43:auto_generated|pll1" output port clk[3] feeds output pin "ATxp[1]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
quartus/harena.fit.rpt:Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/harena.fit.rpt:Warning (169064): Following 14 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
quartus/harena.fit.rpt:Info: Quartus II 32-bit Fitter was successful. 0 errors, 19 warnings
quartus/harena.map.rpt:; monitor ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/harena.map.rpt:; rxs_valid ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/harena.map.rpt:; wb ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/harena.map.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/harena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/serializer.v(188)
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at countbits.v(24): Parameter Declaration in module "countbits" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at aarena.v(51): Parameter Declaration in module "aarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at aarena.v(52): Parameter Declaration in module "aarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at aarena.v(53): Parameter Declaration in module "aarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at aarena.v(54): Parameter Declaration in module "aarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at aarena.v(148): Parameter Declaration in module "aarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at aarena.v(181): Parameter Declaration in module "aarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(270): Parameter Declaration in module "dorn_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(271): Parameter Declaration in module "dorn_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(272): Parameter Declaration in module "dorn_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(273): Parameter Declaration in module "dorn_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(274): Parameter Declaration in module "dorn_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(275): Parameter Declaration in module "dorn_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(44): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(50): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(51): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(66): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(67): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(68): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(69): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(111): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(130): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(131): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ahepam_ana_core.v(132): Parameter Declaration in module "ahepam_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at arena.v(166): truncated value with size 32 to match size of target (7)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at arena.v(228): truncated value with size 32 to match size of target (7)
quartus/harena.map.rpt:Warning (10034): Output port "debug[4..6]" at arena.v(73) has no driver
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(256): truncated value with size 32 to match size of target (8)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(258): truncated value with size 32 to match size of target (8)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(151): truncated value with size 32 to match size of target (10)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(172): truncated value with size 32 to match size of target (10)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at aarena.v(194): truncated value with size 32 to match size of target (16)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at aarena.v(196): truncated value with size 32 to match size of target (16)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at aarena.v(222): truncated value with size 32 to match size of target (16)
quartus/harena.map.rpt:Warning (10665): Bidirectional port "stats[3]" at aarena.v(12) has a one-way connection to bidirectional port "errors[3]"
quartus/harena.map.rpt:Warning (10665): Bidirectional port "stats[2]" at aarena.v(12) has a one-way connection to bidirectional port "errors[2]"
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at secondcyclone.v(133): truncated value with size 32 to match size of target (5)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at ahepam_ana_core.v(285): truncated value with size 32 to match size of target (8)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at ahepam_ana_core.v(296): truncated value with size 32 to match size of target (8)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at ahepam_ana_core.v(302): truncated value with size 32 to match size of target (8)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at ahepam_ana_core.v(308): truncated value with size 32 to match size of target (8)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at secondcyclone.v(49): truncated value with size 32 to match size of target (8)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at secondcyclone.v(60): truncated value with size 32 to match size of target (5)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_master_adc.v(99): truncated value with size 32 to match size of target (4)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc_data.v(27): truncated value with size 32 to match size of target (2)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at oscilloscope.v(78): truncated value with size 32 to match size of target (12)
quartus/harena.map.rpt:Warning (10230): Verilog HDL assignment warning at oscilloscope.v(140): truncated value with size 32 to match size of target (16)
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|stats[15]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|stats[14]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|stats[13]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|stats[12]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|stats[11]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|stats[10]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|stats[9]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|stats[8]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|stats[7]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|stats[6]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|stats[5]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|stats[4]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|stats[0]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|errors[15]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|errors[14]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|errors[13]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|errors[12]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|errors[11]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|errors[10]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|errors[9]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|errors[8]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|errors[7]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|errors[6]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|errors[5]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|errors[4]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|errors[1]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (12161): Node "aarena:core|errors[0]" is stuck at GND because node is in wire loop and does not have a source
quartus/harena.map.rpt:Warning (14284): Synthesized away the following node(s):
quartus/harena.map.rpt: Warning (14285): Synthesized away the following RAM node(s):
quartus/harena.map.rpt:Warning (13024): Output pins are stuck at VCC or GND
quartus/harena.map.rpt: Warning (13410): Pin "attn" is stuck at VCC
quartus/harena.map.rpt: Warning (13410): Pin "ATxp[4]" is stuck at GND
quartus/harena.map.rpt: Warning (13410): Pin "ATxp[2]" is stuck at GND
quartus/harena.map.rpt: Warning (13410): Pin "ATxn[4]" is stuck at GND
quartus/harena.map.rpt: Warning (13410): Pin "ATxn[2]" is stuck at GND
quartus/harena.map.rpt: Warning (13410): Pin "debug[6]" is stuck at GND
quartus/harena.map.rpt: Warning (13410): Pin "debug[5]" is stuck at GND
quartus/harena.map.rpt: Warning (13410): Pin "debug[4]" is stuck at GND
quartus/harena.map.rpt: Warning (13410): Pin "debug[3]" is stuck at GND
quartus/harena.map.rpt: Warning (13410): Pin "debug[1]" is stuck at GND
quartus/harena.map.rpt:Warning (15899): PLL "pll96:pll0|altpll:altpll_component|altpll_lm43:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
quartus/harena.map.rpt:Warning (21074): Design contains 4 input pin(s) that do not drive logic
quartus/harena.map.rpt: Warning (15610): No output dependent on input pin "clk_T1"
quartus/harena.map.rpt: Warning (15610): No output dependent on input pin "Rx[4]"
quartus/harena.map.rpt: Warning (15610): No output dependent on input pin "Rx[3]"
quartus/harena.map.rpt: Warning (15610): No output dependent on input pin "ARx[1]"
