solo_altera/arena/altera/sarena.warnings

sarena.asm.rpt:Info: Quartus II Assembler was successful. 0 errors, 0 warnings
sarena.fit.rpt:  5. I/O Assignment Warnings
sarena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
sarena.fit.rpt:; I/O Assignment Warnings                         ;
sarena.fit.rpt:Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
sarena.fit.rpt:Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
sarena.fit.rpt:Warning: Following 8 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
sarena.fit.rpt:    Warning: Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
sarena.fit.rpt:    Warning: Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
sarena.fit.rpt:    Warning: Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
sarena.fit.rpt:    Warning: Pin "adc_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "adc_clk(n)"
sarena.fit.rpt:    Warning: Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
sarena.fit.rpt:    Warning: Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
sarena.fit.rpt:    Warning: Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
sarena.fit.rpt:    Warning: Pin "ARTx" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARTx(n)"
sarena.fit.rpt:Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
sarena.fit.rpt:Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
sarena.fit.rpt:Warning: Following 14 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
sarena.fit.rpt:Info: Quartus II Fitter was successful. 0 errors, 14 warnings
sarena.map.rpt:; rbi     ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (1 bits) it drives.  The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
sarena.map.rpt:; halffull ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
sarena.map.rpt:; c1   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
sarena.map.rpt:; c2   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
sarena.map.rpt:; c3   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
sarena.map.rpt:; c4   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
sarena.map.rpt:Warning (10236): Verilog HDL Implicit Net warning at arena.v(212): created implicit net for "tick_reset"
sarena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at arena.v(212): object "tick_reset" assigned a value but never read
sarena.map.rpt:Warning (10034): Output port "debug" at arena.v(37) has no driver
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(101): truncated value with size 32 to match size of target (4)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(259): truncated value with size 32 to match size of target (8)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(261): truncated value with size 32 to match size of target (8)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(83): truncated value with size 32 to match size of target (3)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(137): truncated value with size 32 to match size of target (10)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(43): truncated value with size 32 to match size of target (6)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(81): truncated value with size 32 to match size of target (6)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(117): truncated value with size 32 to match size of target (12)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(135): truncated value with size 32 to match size of target (8)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(176): truncated value with size 32 to match size of target (5)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(178): truncated value with size 32 to match size of target (5)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(201): truncated value with size 32 to match size of target (7)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(245): truncated value with size 32 to match size of target (16)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(277): truncated value with size 32 to match size of target (4)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(281): truncated value with size 32 to match size of target (4)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(286): truncated value with size 32 to match size of target (4)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(320): truncated value with size 32 to match size of target (3)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(325): truncated value with size 32 to match size of target (3)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(330): truncated value with size 32 to match size of target (3)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(381): truncated value with size 32 to match size of target (16)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(386): truncated value with size 32 to match size of target (16)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(391): truncated value with size 32 to match size of target (16)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(412): truncated value with size 32 to match size of target (4)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at sixs.v(419): truncated value with size 32 to match size of target (8)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_master_adc.v(99): truncated value with size 32 to match size of target (4)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc_data.v(25): truncated value with size 32 to match size of target (2)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at oscilloscope.v(75): truncated value with size 32 to match size of target (10)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at logicanalyser.v(74): truncated value with size 32 to match size of target (10)
sarena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(28): truncated value with size 32 to match size of target (15)
sarena.map.rpt:Warning: Synthesized away the following node(s):
sarena.map.rpt:    Warning: Synthesized away the following RAM node(s):
sarena.map.rpt:        Warning (14320): Synthesized away node "sarena:core|logicanalyser:lana|spififo:buffer|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[14]"
sarena.map.rpt:        Warning (14320): Synthesized away node "sarena:core|oscilloscope:scope|spififo:buffer|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15]"
sarena.map.rpt:Warning: 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
sarena.map.rpt:Warning: The following nodes have both tri-state and non-tri-state drivers
sarena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[3]" and its non-tri-state driver.
sarena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[5]" and its non-tri-state driver.
sarena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[7]" and its non-tri-state driver.
sarena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[8]" and its non-tri-state driver.
sarena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[9]" and its non-tri-state driver.
sarena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[10]" and its non-tri-state driver.
sarena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[11]" and its non-tri-state driver.
sarena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[12]" and its non-tri-state driver.
sarena.map.rpt:Warning: The following bidir pins have no drivers
sarena.map.rpt:    Warning: Bidir "adc_mode" has no driver
sarena.map.rpt:    Warning: Bidir "AC[0]" has no driver
sarena.map.rpt:    Warning: Bidir "AC[1]" has no driver
sarena.map.rpt:    Warning: Bidir "AC[6]" has no driver
sarena.map.rpt:Warning: The following tri-state nodes are fed by constants
sarena.map.rpt:    Warning: The pin "AC[2]" is fed by GND
sarena.map.rpt:    Warning: The pin "AC[4]" is fed by GND
sarena.map.rpt:Warning: TRI or OPNDRN buffers permanently enabled
sarena.map.rpt:    Warning: Node "AC[3]~synth"
sarena.map.rpt:    Warning: Node "AC[5]~synth"
sarena.map.rpt:    Warning: Node "AC[7]~synth"
sarena.map.rpt:    Warning: Node "AC[8]~synth"
sarena.map.rpt:    Warning: Node "AC[9]~synth"
sarena.map.rpt:    Warning: Node "AC[10]~synth"
sarena.map.rpt:    Warning: Node "AC[11]~synth"
sarena.map.rpt:    Warning: Node "AC[12]~synth"
sarena.map.rpt:Warning: Output pins are stuck at VCC or GND
sarena.map.rpt:    Warning (13410): Pin "debug[6]" is stuck at GND
sarena.map.rpt:    Warning (13410): Pin "debug[5]" is stuck at GND
sarena.map.rpt:    Warning (13410): Pin "debug[4]" is stuck at GND
sarena.map.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
sarena.map.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
sarena.map.rpt:Warning: Design contains 4 input pin(s) that do not drive logic
sarena.map.rpt:    Warning (15610): No output dependent on input pin "clk_T1"
sarena.map.rpt:    Warning (15610): No output dependent on input pin "trigger"
sarena.map.rpt:    Warning (15610): No output dependent on input pin "Rx[4]"
sarena.map.rpt:    Warning (15610): No output dependent on input pin "Rx[3]"
sarena.map.rpt:Info: Quartus II Analysis & Synthesis was successful. 0 errors, 75 warnings
sarena.sta.rpt:Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings