solo_altera/arena/altera/varena.warnings

varena.asm.rpt:Info: Quartus II Assembler was successful. 0 errors, 0 warnings
varena.fit.rpt:  5. I/O Assignment Warnings
varena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
varena.fit.rpt:; I/O Assignment Warnings                         ;
varena.fit.rpt:Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
varena.fit.rpt:Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
varena.fit.rpt:Warning: Following 11 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
varena.fit.rpt:    Warning: Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
varena.fit.rpt:    Warning: Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
varena.fit.rpt:    Warning: Pin "adc_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "adc_clk(n)"
varena.fit.rpt:    Warning: Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
varena.fit.rpt:    Warning: Pin "ARTx" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARTx(n)"
varena.fit.rpt:    Warning: Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
varena.fit.rpt:    Warning: Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
varena.fit.rpt:    Warning: Pin "ARx[3]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[3](n)"
varena.fit.rpt:    Warning: Pin "ARx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[1](n)"
varena.fit.rpt:    Warning: Pin "ARx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[2](n)"
varena.fit.rpt:    Warning: Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
varena.fit.rpt:Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
varena.fit.rpt:Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
varena.fit.rpt:Warning: Following 14 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
varena.fit.rpt:Info: Quartus II Fitter was successful. 0 errors, 17 warnings
varena.map.rpt:; rbi     ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (1 bits) it drives.  The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
varena.map.rpt:; halffull ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
varena.map.rpt:; c1   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
varena.map.rpt:; c2   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
varena.map.rpt:; c3   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
varena.map.rpt:; c4   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at arena.v(109): truncated value with size 32 to match size of target (7)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(101): truncated value with size 32 to match size of target (4)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(259): truncated value with size 32 to match size of target (8)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(261): truncated value with size 32 to match size of target (8)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(83): truncated value with size 32 to match size of target (3)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(137): truncated value with size 32 to match size of target (10)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at varena.v(181): truncated value with size 32 to match size of target (16)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at virena_conf.v(23): truncated value with size 32 to match size of target (6)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at virena_conf.v(25): truncated value with size 32 to match size of target (6)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at virena_conf.v(50): truncated value with size 32 to match size of target (6)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at vl1trig.v(64): truncated value with size 32 to match size of target (16)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at conf_reg.v(122): truncated value with size 32 to match size of target (16)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at vl1trig.v(217): truncated value with size 32 to match size of target (16)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at vl2trig.v(136): truncated value with size 32 to match size of target (16)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at vl2trig.v(41): truncated value with size 32 to match size of target (6)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at vl2trig.v(265): truncated value with size 32 to match size of target (8)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at confmem.v(38): truncated value with size 32 to match size of target (16)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_master_adc.v(99): truncated value with size 32 to match size of target (4)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc_data.v(25): truncated value with size 32 to match size of target (2)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at vl3trig.v(44): truncated value with size 32 to match size of target (6)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at vl3trig.v(82): truncated value with size 32 to match size of target (8)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at vl3trig.v(155): truncated value with size 32 to match size of target (16)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at vl3trig.v(197): truncated value with size 32 to match size of target (6)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at vl3trig.v(219): truncated value with size 32 to match size of target (9)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at vl3trig.v(221): truncated value with size 32 to match size of target (9)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at vl1trig.v(136): truncated value with size 32 to match size of target (8)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at vl1trig.v(180): truncated value with size 32 to match size of target (8)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at oscilloscope.v(75): truncated value with size 32 to match size of target (10)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(38): truncated value with size 32 to match size of target (7)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(57): truncated value with size 32 to match size of target (20)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(77): truncated value with size 32 to match size of target (15)
varena.map.rpt:Warning (10230): Verilog HDL assignment warning at logicanalyser.v(74): truncated value with size 32 to match size of target (10)
varena.map.rpt:Warning: Synthesized away the following node(s):
varena.map.rpt:    Warning: Synthesized away the following RAM node(s):
varena.map.rpt:        Warning (14320): Synthesized away node "varena:core|logicanalyser:lana|spififo:buffer|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[14]"
varena.map.rpt:        Warning (14320): Synthesized away node "varena:core|oscilloscope:scope|spififo:buffer|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15]"
varena.map.rpt:Warning: 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
varena.map.rpt:Warning: The following nodes have both tri-state and non-tri-state drivers
varena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[0]" and its non-tri-state driver.
varena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[1]" and its non-tri-state driver.
varena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[3]" and its non-tri-state driver.
varena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[4]" and its non-tri-state driver.
varena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[5]" and its non-tri-state driver.
varena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[6]" and its non-tri-state driver.
varena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[7]" and its non-tri-state driver.
varena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[8]" and its non-tri-state driver.
varena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[9]" and its non-tri-state driver.
varena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[10]" and its non-tri-state driver.
varena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[11]" and its non-tri-state driver.
varena.map.rpt:    Warning: Inserted always-enabled tri-state buffer between "AC[12]" and its non-tri-state driver.
varena.map.rpt:Warning: The following bidir pins have no drivers
varena.map.rpt:    Warning: Bidir "adc_mode" has no driver
varena.map.rpt:Warning: The following tri-state nodes are fed by constants
varena.map.rpt:    Warning: The pin "AC[2]" is fed by GND
varena.map.rpt:Warning: TRI or OPNDRN buffers permanently enabled
varena.map.rpt:    Warning: Node "AC[0]~synth"
varena.map.rpt:    Warning: Node "AC[1]~synth"
varena.map.rpt:    Warning: Node "AC[3]~synth"
varena.map.rpt:    Warning: Node "AC[4]~synth"
varena.map.rpt:    Warning: Node "AC[5]~synth"
varena.map.rpt:    Warning: Node "AC[6]~synth"
varena.map.rpt:    Warning: Node "AC[7]~synth"
varena.map.rpt:    Warning: Node "AC[8]~synth"
varena.map.rpt:    Warning: Node "AC[9]~synth"
varena.map.rpt:    Warning: Node "AC[10]~synth"
varena.map.rpt:    Warning: Node "AC[11]~synth"
varena.map.rpt:    Warning: Node "AC[12]~synth"
varena.map.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
varena.map.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
varena.map.rpt:Warning: Design contains 3 input pin(s) that do not drive logic
varena.map.rpt:    Warning (15610): No output dependent on input pin "clk_T1"
varena.map.rpt:    Warning (15610): No output dependent on input pin "Rx[4]"
varena.map.rpt:    Warning (15610): No output dependent on input pin "Rx[3]"
varena.map.rpt:Info: Quartus II Analysis & Synthesis was successful. 0 errors, 74 warnings
varena.sta.rpt:Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings