solo_altera/change4/altera/Makefile

VERILOG=/usr/local/bin/iverilog
VVP=$(subst iverilog,vvp,$(VERILOG))
#VERILOG=/usr/bin/iverilog

VERILOGFLAGS = -v -Wall -Wno-timescale -DSIMULATION $($*_FLAGS)
%.vvp: %.v
	-grep TODO $(filter %.v,$^) > TODO.$*
	$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v,$^)

vcd/%.lxt: %.vvp
	$(VVP) -v $< -lxt2 | tee $*.log

.PRECIOUS: vcd/%.lxt

VPATH=../../arena/altera:../../areana/altera/adc128:\
../../irena/altera/adc128:../../hetept/altera:\
../../sirena/altera:../../sirena/altera/l3:../../sirena/altera/encode:\
../../altera:../../altera/mega:../../altera/actel

sirena_ana_FLAGS = -ssirena_ana_test -DSIRENA_ANA_TEST -DANA_CORE -DREMOTE_ADC -DGENSRAM -DSER_FIFO_ALTERA
sirena_ana.vvp:  sirena_ana.v heteptana.v \
	serializer.v spififo_sim.v conf_reg.v itof.v secondcyclone.v \
	sfilter.v adc128s102.v hkadc.v opheater.v

ce4ana_FLAGS = -sce4ana_test -DCE4ANA_TEST -DANA_CORE -DREMOTE_ADC -DGENSRAM -DSER_FIFO_ALTERA
ce4ana.vvp:  ce4ana.v heteptana.v \
	serializer.v spififo_sim.v conf_reg.v itof.v secondcyclone.v \
	sfilter.v adc128s102.v hkadc.v actel.v

ce4dig_RAM = -DACTEL_SRAM -DSEU_RATE=50
ce4dig_SRAM = -DMEM16EE 
ce4dig_OPTIONS =
ce4dig_FLAGS = -s ce4dig_test $(ce4dig_OPTIONS) \
 -DChangE4 -DREMOTE_ADC -DNO_MSG_TIMEOUT -DUART_PARITY=1 \
 -DCE4DIG_TEST -DHETEPTANA_TEST \
 -DARxSTREAM \
 -DUART3MHZ -DM24MHZ $(ce4dig_RAM) $(ce4dig_SRAM)

QUARTUS=/usr/local/quartus/altera13.1/quartus
export PATH:=$(PATH):$(QUARTUS)/bin
QUARTUS_OUTPUT=quartus

$(QUARTUS_OUTPUT)/%.rbf: %.qpf %.qsf %.sdc
	quartus_map $<
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning $(QUARTUS_OUTPUT)/$*.*.rpt \
          | grep -v 'truncated value with size 32 to match size of target' > $*.warnings

FRONTEND = conf_reg.v spi_slave.v pll96.v spififo.v frontend.v packetfifo.v

$(QUARTUS_OUTPUT)/sirena_ana.rbf: sirena_ana.v pll240d_96.v spififo.v conf_reg.v \
	heteptana.v serializer.v itof.v secondcyclone.v sfilter.v adc128s102.v hkadc.v opheater.v