quartus/sirena_ana.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/sirena_ana.fit.rpt:Warning (15536): Implemented PLL "pll240d_96:pll1|altpll:altpll_component|altpll_tu53:auto_generated|pll1" as Cyclone IV E PLL type, but with warnings
quartus/sirena_ana.fit.rpt: Warning (15559): Can't achieve requested value 69.1 degrees for clock output pll240d_96:pll1|altpll:altpll_component|altpll_tu53:auto_generated|clk[4] of parameter phase shift -- achieved value of 67.5 degrees
quartus/sirena_ana.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
quartus/sirena_ana.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
quartus/sirena_ana.fit.rpt:Warning (176674): Following 12 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
quartus/sirena_ana.fit.rpt: Warning (176118): Pin "ARxP[4]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARxP[4](n)"
quartus/sirena_ana.fit.rpt: Warning (176118): Pin "ARxP[3]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARxP[3](n)"
quartus/sirena_ana.fit.rpt: Warning (176118): Pin "ARxP[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARxP[2](n)"
quartus/sirena_ana.fit.rpt: Warning (176118): Pin "ARxP[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARxP[1](n)"
quartus/sirena_ana.fit.rpt: Warning (176118): Pin "ATxP[5]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ATxP[5](n)"
quartus/sirena_ana.fit.rpt: Warning (176118): Pin "ATxP[4]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ATxP[4](n)"
quartus/sirena_ana.fit.rpt: Warning (176118): Pin "ATxP[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ATxP[2](n)"
quartus/sirena_ana.fit.rpt: Warning (176118): Pin "SCLK_n" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "SCLK_n(n)"
quartus/sirena_ana.fit.rpt: Warning (176118): Pin "CS_n" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "CS_n(n)"
quartus/sirena_ana.fit.rpt: Warning (176118): Pin "ATxP[3]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ATxP[3](n)"
quartus/sirena_ana.fit.rpt: Warning (176118): Pin "ATxP[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ATxP[1](n)"
quartus/sirena_ana.fit.rpt: Warning (176118): Pin "DCLK_p" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "DCLK_p(n)"
quartus/sirena_ana.fit.rpt:Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/sirena_ana.fit.rpt:Warning (176251): Ignoring some wildcard destinations of fast I/O register assignments
quartus/sirena_ana.fit.rpt:Warning (15064): PLL "pll240d_96:pll1|altpll:altpll_component|altpll_tu53:auto_generated|pll1" output port clk[4] feeds output pin "top_pads[1]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
quartus/sirena_ana.fit.rpt:Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/sirena_ana.fit.rpt:Warning (169177): 81 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
quartus/sirena_ana.fit.rpt:Warning (169064): Following 45 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
quartus/sirena_ana.map.rpt:; dutycycle ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/sirena_ana.map.rpt:; duration ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/sirena_ana.map.rpt:; CSn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/sirena_ana.map.rpt:; SCLKn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/sirena_ana.map.rpt:; dout1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/sirena_ana.map.rpt:; dine ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/sirena_ana.map.rpt:; n ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/sirena_ana.map.rpt:; rrn ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (7 bits) it drives. The 25 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
quartus/sirena_ana.map.rpt:; dout1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/sirena_ana.map.rpt:; doute ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/sirena_ana.map.rpt:; din1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/sirena_ana.map.rpt:; dine ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/sirena_ana.map.rpt:; c1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/sirena_ana.map.rpt:; c2 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/sirena_ana.map.rpt:; c3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/sirena_ana.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1530): truncated value with size 30 to match size of target (16)
quartus/sirena_ana.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1581): truncated value with size 3 to match size of target (2)
quartus/sirena_ana.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1592): truncated value with size 4 to match size of target (3)
quartus/sirena_ana.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1594): truncated value with size 4 to match size of target (3)
quartus/sirena_ana.map.rpt:Warning (10230): Verilog HDL assignment warning at opheater.v(37): truncated value with size 4 to match size of target (3)
quartus/sirena_ana.map.rpt:Warning (10230): Verilog HDL assignment warning at opheater.v(40): truncated value with size 16 to match size of target (13)
quartus/sirena_ana.map.rpt: Warning (13410): Pin "A[0]" is stuck at GND
quartus/sirena_ana.map.rpt: Warning (13410): Pin "A[1]" is stuck at GND
quartus/sirena_ana.map.rpt: Warning (13410): Pin "A[2]" is stuck at GND
quartus/sirena_ana.map.rpt: Warning (13410): Pin "A[3]" is stuck at GND
quartus/sirena_ana.map.rpt: Warning (13410): Pin "A[4]" is stuck at GND
quartus/sirena_ana.map.rpt: Warning (13410): Pin "A[5]" is stuck at GND
quartus/sirena_ana.map.rpt: Warning (13410): Pin "A[6]" is stuck at GND
quartus/sirena_ana.map.rpt: Warning (13410): Pin "A[7]" is stuck at GND
quartus/sirena_ana.map.rpt: Warning (13410): Pin "A22" is stuck at GND
quartus/sirena_ana.map.rpt:Warning (15899): PLL "pll240d_96:pll1|altpll:altpll_component|altpll_tu53:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
