rpigse.asm.rpt:Info: Quartus II Assembler was successful. 0 errors, 0 warnings
rpigse.fit.rpt: 5. I/O Assignment Warnings
rpigse.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
rpigse.fit.rpt:; I/O Assignment Warnings ;
rpigse.fit.rpt:Warning: PLL "pll384:pll0|altpll:altpll_component|altpll_c433:auto_generated|pll1" has parameter clk1_counter set to C1 specified but port CLK[1] is not connected
rpigse.fit.rpt:Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
rpigse.fit.rpt:Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
rpigse.fit.rpt:Warning: Following 4 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
rpigse.fit.rpt: Warning: Pin "LRTx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRTx[2](n)"
rpigse.fit.rpt: Warning: Pin "LRTx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRTx[1](n)"
rpigse.fit.rpt: Warning: Pin "LRx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRx[2](n)"
rpigse.fit.rpt: Warning: Pin "LRx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRx[1](n)"
rpigse.fit.rpt:Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
rpigse.fit.rpt:Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
rpigse.fit.rpt:Warning: 41 pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems).
rpigse.fit.rpt:Warning: PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447.
rpigse.fit.rpt:Warning: Following 33 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
rpigse.map.rpt:; dout1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
rpigse.map.rpt:; dine ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
rpigse.map.rpt:; n ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
rpigse.map.rpt:; Tx_busy ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
rpigse.map.rpt:; Tx_full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
rpigse.map.rpt:; Rx_busy ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
rpigse.map.rpt:; Rx_brk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
rpigse.map.rpt:; Rx_attn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
rpigse.map.rpt:; rbi ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
rpigse.map.rpt:; halffull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
rpigse.map.rpt:; attn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
rpigse.map.rpt:; c1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
rpigse.map.rpt:; c4 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
rpigse.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(128): Parameter Declaration in module "pps_gen" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
rpigse.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(129): Parameter Declaration in module "pps_gen" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
rpigse.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(96): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
rpigse.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(97): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
rpigse.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(98): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
rpigse.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(99): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
rpigse.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(100): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
rpigse.map.rpt:Warning: Output pins are stuck at VCC or GND
rpigse.map.rpt: Warning (13410): Pin "SCLK[4]" is stuck at GND
rpigse.map.rpt: Warning (13410): Pin "SCLK[3]" is stuck at GND
rpigse.map.rpt: Warning (13410): Pin "SCLK[2]" is stuck at GND
rpigse.map.rpt: Warning (13410): Pin "SCLK[1]" is stuck at GND
rpigse.map.rpt: Warning (13410): Pin "nCS[4]" is stuck at VCC
rpigse.map.rpt: Warning (13410): Pin "nCS[3]" is stuck at VCC
rpigse.map.rpt: Warning (13410): Pin "nCS[2]" is stuck at VCC
rpigse.map.rpt: Warning (13410): Pin "nCS[1]" is stuck at VCC
rpigse.map.rpt:Warning: PLL "pll384:pll0|altpll:altpll_component|altpll_c433:auto_generated|pll1" has parameter clk1_counter set to C1 specified but port CLK[1] is not connected
rpigse.map.rpt:Warning: PLL "pll384:pll0|altpll:altpll_component|altpll_c433:auto_generated|pll1" has parameter clk1_counter set to C1 specified but port CLK[1] is not connected
