2020-03-01 22:53:54 +00:00
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2024-02-20 23:04:11 +00:00
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VERILOG=/usr/bin/iverilog
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2020-03-01 22:53:54 +00:00
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#VERILOG=/usr/bin/iverilog
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VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
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%.vvp:
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2024-03-12 12:32:55 +00:00
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$(VERILOG) $(VERILOGFLAGS) $(VFLAGS) -o $@ $^
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2020-03-01 22:53:54 +00:00
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2024-05-17 09:36:09 +00:00
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vcd/%.fst: %.vvp
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2024-05-17 09:34:36 +00:00
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$< -fst | tee $*.log
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2020-03-01 22:53:54 +00:00
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2024-11-18 16:46:16 +00:00
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.PRECIOUS: vcd/%.fst
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2020-03-01 22:53:54 +00:00
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2024-02-20 23:04:11 +00:00
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VPATH=.:../../altera:../../altera/mega:../../irena/altera:../../arena/altera:\
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2024-11-14 11:55:07 +00:00
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../../nm64/altera:../../irena/altera/adc128:../../sirena/altera:\
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../../sirena/altera/l3:../../dorn/altera
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2020-03-01 22:53:54 +00:00
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2020-03-20 03:01:34 +00:00
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DARENA_SRC = darena.v arena.v dorn.v dmem.v adc128s102.v \
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2020-03-31 23:47:58 +00:00
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frontend.v frontend_test.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v scangen.v \
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2020-03-11 04:29:32 +00:00
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countbits.v pulser.v dornpulse.v divider.v \
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2020-03-12 23:59:28 +00:00
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ltc2656.v adc_data.v oscilloscope.v spi_master_adc.v ad9649.v
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2020-03-01 22:53:54 +00:00
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2020-03-20 03:01:34 +00:00
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$(patsubst %,vsrc/%,$(DARENA_SRC)): $(DARENA_SRC)
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mkdir -p vsrc
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cp -puv $^ vsrc
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2020-03-01 22:53:54 +00:00
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darena.vvp: $(DARENA_SRC)
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2020-03-20 03:01:34 +00:00
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darena_FLAGS = -sdarena_test -DDARENA -DDARENA_TEST -DDORN_SRAM -DWITH_FULL_L2_CONF -DWITH_FULL_L3_CONF
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2020-03-01 22:53:54 +00:00
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2024-02-20 23:04:11 +00:00
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stis_ana_core.vvp: stis_ana_core.v dorn.v multiply.v divider.v dmem.v \
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conf_reg.v packetfifo.v spififo_sim.v countbits.v \
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serializer.v secondcyclone.v memport.v log7to4.v \
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pulser.v adc128s102.v adc_data.v
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stis_ana_core_FLAGS = -sstis_ana_core_test -DSTIS_ANA_CORE_TEST \
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-DINFERRED_SRAM -DSER_FIFO_ALTERA \
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2024-09-16 18:00:09 +00:00
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-DWITH_FULL_L1_CONF -DWITH_FULL_L2_CONF -DWITH_FULL_L3_CONF \
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-DWITH_DORN_L4 -DWITH_DORN_SC
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2024-02-20 23:04:11 +00:00
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2024-02-26 18:37:30 +00:00
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stis_ana_demo.vvp: stis_ana_demo.v \
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stis_ana_core.v dorn.v multiply.v divider.v dmem.v \
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conf_reg.v packetfifo.v spififo_sim.v countbits.v \
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serializer.v secondcyclone.v memport.v log7to4.v \
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pulser.v adc128s102.v adc_data.v
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stis_ana_demo_FLAGS = -sstis_ana_demo_test -DSTIS_ANA_DEMO_TEST -DSTIS_ANA_JIG \
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-DINFERRED_SRAM -DSER_FIFO_ALTERA -DHAVE_GSE_PORT \
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2024-09-16 18:00:09 +00:00
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-DWITH_FULL_L1_CONF -DWITH_FULL_L2_CONF -DWITH_FULL_L3_CONF \
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-DWITH_DORN_L4 -DWITH_DORN_SC
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2024-02-26 18:37:30 +00:00
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2024-10-17 12:05:43 +00:00
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nmahepam.vvp: nmahepam.v pll192_sim.v pll192_test.v frontend_test.v \
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2024-11-13 17:35:22 +00:00
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spi_slave.v frontend.v conf_reg.v packetfifo.v spififo_sim.v countbits.v \
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2025-03-01 23:27:34 +00:00
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stis_ana_core.v slow_clock.v nmcounter.v mem.v itof.v ms5540c.v \
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2025-03-02 20:18:57 +00:00
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dorn.v adc128s102.v pulser.v divider.v multiply.v dmem.v i2c.v
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2024-09-24 11:53:56 +00:00
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2024-10-15 13:59:10 +00:00
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nmahepam_FLAGS = -s nmahepam_test -DNMAHEPAM_TEST -DNMRENA_v2 -DINFERRED_SRAM \
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2024-11-13 17:35:22 +00:00
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-DWITH_FULL_L1_CONF -DWITH_FULL_L2_CONF -DWITH_FULL_L3_CONF \
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2025-02-19 08:04:24 +00:00
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-DSTIS_ANA_JIG -DANA_WITHOUT_SERIALIZER \
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2025-03-02 20:18:57 +00:00
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-DSPARSE_TRIG_EN -DWITH_GTRIGGER -DL2_AHEPAM -DPLL_TEST
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2024-09-24 11:53:56 +00:00
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2024-10-17 12:05:43 +00:00
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CYCLONE=10
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2024-02-26 18:37:30 +00:00
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ifeq ($(CYCLONE),10)
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QUARTUS=/usr/local/quartus/intelFPGA_lite/20.1/quartus
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else
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2020-03-01 22:53:54 +00:00
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QUARTUS=/usr/local/quartus/altera13.1/quartus
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2024-02-26 18:37:30 +00:00
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endif
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2024-10-17 12:05:43 +00:00
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export PATH:=$(QUARTUS)/bin:$(PATH):.
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2020-03-01 22:53:54 +00:00
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2024-02-26 18:37:30 +00:00
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ifeq ($(CYCLONE),)
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%_c3.rbf: %_c3.qsf
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$(MAKE) CYCLONE=3 $@
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%_c10.rbf: %_c10.qsf
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$(MAKE) CYCLONE=10 $@
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else
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%_c$(CYCLONE).qpf: %.qpf
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ln $< $@
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%_c$(CYCLONE).sdc: %.sdc
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ln $< $@
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endif
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2024-03-05 22:04:23 +00:00
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MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS) $(MAPDEFS))
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2020-03-01 22:53:54 +00:00
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QDIR=quartus
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$(QDIR)/%.rbf: %.qpf %.qsf %.sdc \
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frontend.v spi_slave.v conf_reg.v packetfifo.v spififo.v
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quartus_map $< $(MAPFLGS)
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quartus_fit $<
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quartus_asm $<
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quartus_sta $<
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2025-02-16 16:15:15 +00:00
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grep -i warning $(QDIR)/$*.*.rpt \
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| grep -v 'behaves as a Local Parameter Declaration because the module' \
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| grep -v 'truncated value with size 32 to match size of target' \
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| sed 's/\.v([0-9]\+)/.v(…)/;s/File: .* Line: [0-9]\+$$//' \
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> $*.warnings
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2025-03-02 20:18:57 +00:00
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grep '^; -' $(QDIR)/$*.sta.rpt >> $*.warnings || echo Timing OK
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2020-03-01 22:53:54 +00:00
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$(QDIR)/darena.rbf: pll96.v arena.v dorn.v \
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ltc2656.v
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2025-03-03 01:24:26 +00:00
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divide_FLAGS= -s divide_test -DDIVIDE_TEST
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2025-03-01 23:04:58 +00:00
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divide.vvp: divider.v multiply.v
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2022-02-26 20:51:25 +00:00
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2022-02-26 21:54:05 +00:00
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multiply_FLAGS= -s multiply_test -DMULTIPLY_TEST -DINFERRED_MULTILIER
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2022-02-26 20:51:25 +00:00
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multiply.vvp: multiply.v
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2022-03-09 21:15:47 +00:00
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dorn_l2_lockup_FLAGS= -s dorn_l2_lockup -DDORN_L2_LOCKUP -DWITH_FULL_L2_CONF
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dorn_l2_lockup.vvp: dorn.v multiply.v dmem.v
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2024-02-26 18:37:30 +00:00
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$(QDIR)/stis_ana_demo_c$(CYCLONE).rbf: stis_ana_demo.v stis_ana_core.v \
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secondcyclone.v serializer.v spififo.v conf_reg.v itof.v \
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packetfifo.v adc128s102.v conf_reg.v countbits.v mem.v \
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dorn.v dmem.v divider.v log7to4.v memport.v
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2024-10-17 12:05:43 +00:00
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$(QDIR)/nmahepam.rbf: nmahepam.v pll192_test.v frontend_test.v \
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2025-02-16 16:15:15 +00:00
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spi_slave.v frontend.v conf_reg.v packetfifo.v countbits.v \
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stis_ana_core.v dorn.v
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2025-11-05 14:43:22 +00:00
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$(QDIR)/nmleia.rbf: nmahepam.v pll192_test.v frontend_test.v \
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spi_slave.v frontend.v conf_reg.v packetfifo.v countbits.v \
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stis_ana_core.v dorn.v
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