272 lines
66 KiB
Text
272 lines
66 KiB
Text
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quartus/stis_ana_demo_c10.asm.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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quartus/stis_ana_demo_c10.asm.rpt:Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
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quartus/stis_ana_demo_c10.fit.rpt: 19. I/O Assignment Warnings
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quartus/stis_ana_demo_c10.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
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quartus/stis_ana_demo_c10.fit.rpt:; I/O Assignment Warnings ;
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quartus/stis_ana_demo_c10.fit.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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quartus/stis_ana_demo_c10.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
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quartus/stis_ana_demo_c10.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
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quartus/stis_ana_demo_c10.fit.rpt:Warning (176674): Following 6 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
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quartus/stis_ana_demo_c10.fit.rpt: Warning (176118): Pin "L_IN[4]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "L_IN[4](n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 23
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quartus/stis_ana_demo_c10.fit.rpt: Warning (176118): Pin "L_IN[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "L_IN[1](n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 23
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quartus/stis_ana_demo_c10.fit.rpt: Warning (176118): Pin "ARxC" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARxC(n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 11
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quartus/stis_ana_demo_c10.fit.rpt: Warning (176118): Pin "L_IN[3]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "L_IN[3](n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 23
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quartus/stis_ana_demo_c10.fit.rpt: Warning (176118): Pin "ARxD" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARxD(n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 11
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quartus/stis_ana_demo_c10.fit.rpt: Warning (176118): Pin "L_IN[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "L_IN[2](n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 23
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quartus/stis_ana_demo_c10.fit.rpt:Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
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quartus/stis_ana_demo_c10.fit.rpt:Warning (176251): Ignoring some wildcard destinations of fast I/O register assignments
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quartus/stis_ana_demo_c10.fit.rpt:Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
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quartus/stis_ana_demo_c10.fit.rpt:Warning (169177): 27 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone 10 LP Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
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quartus/stis_ana_demo_c10.fit.rpt:Warning (169064): Following 14 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
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quartus/stis_ana_demo_c10.fit.rpt:Info: Quartus Prime Fitter was successful. 0 errors, 15 warnings
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quartus/stis_ana_demo_c10.map.rpt:; a ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; d ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; w ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; pend ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; busy ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; a ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; d ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; w ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; ctick ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; a ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; d ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; w ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; ctick ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; RXn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; fempty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; RXn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; fifof ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; fempty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:; lost_sync ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/stis_ana_demo_c10.map.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/serializer.v(188) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/serializer.v Line: 188
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(13) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 13
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(15) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 15
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(63) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 63
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(106) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 106
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(120) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 120
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(556) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 556
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(558) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 558
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(560) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 560
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(565) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 565
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(567) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 567
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(569) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 569
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(584) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 584
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(586) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 586
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(620) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 620
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(982) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 982
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(984) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 984
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(986) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 986
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(988) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 988
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(1084) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 1084
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(1098) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 1098
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(1224) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 1224
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(1226) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 1226
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(1228) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 1228
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(1230) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 1230
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(1332) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 1332
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(1344) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 1344
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quartus/stis_ana_demo_c10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(1356) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 1356
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(40): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 40
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(41): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 41
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(112): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 112
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(133): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 133
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(210): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 210
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(298): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 298
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(535): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 535
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(537): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 537
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(538): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 538
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(539): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 539
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(542): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 542
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(543): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 543
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(544): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 544
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(545): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 545
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(546): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 546
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(556): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 556
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(299): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 299
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(300): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 300
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(301): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 301
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(302): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 302
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(303): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 303
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quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(304): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 304
|
||
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|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(305): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 305
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(307): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 307
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(308): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 308
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(310): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 310
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(311): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 311
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(312): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 312
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(313): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 313
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(314): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 314
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(315): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 315
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(317): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 317
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(318): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 318
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(320): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 320
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(542): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 542
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(543): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 543
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(544): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 544
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(545): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 545
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(546): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 546
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(687): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 687
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(376): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 376
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(793): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 793
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(794): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 794
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(795): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 795
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(796): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 796
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(797): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 797
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(798): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 798
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(799): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 799
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(800): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 800
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(801): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 801
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(802): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 802
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(803): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 803
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(804): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 804
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at multiply.v(10): Parameter Declaration in module "dorn_multiply" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/multiply.v Line: 10
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(498): Parameter Declaration in module "lsb_encode" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 498
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(1069): Parameter Declaration in module "dorn_l3" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1069
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(1070): Parameter Declaration in module "dorn_l3" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1070
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(1071): Parameter Declaration in module "dorn_l3" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1071
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at divider.v(20): Parameter Declaration in module "dorn_divide" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 20
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(1190): Parameter Declaration in module "dorn_l4" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1190
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(1191): Parameter Declaration in module "dorn_l4" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1191
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(1192): Parameter Declaration in module "dorn_l4" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1192
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(1193): Parameter Declaration in module "dorn_l4" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1193
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(640): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 640
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(743): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 743
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(387): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 387
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(396): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 396
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(397): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 397
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(450): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 450
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(457): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 457
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(488): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 488
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(771): Parameter Declaration in module "stis_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 771
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(772): Parameter Declaration in module "stis_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 772
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(773): Parameter Declaration in module "stis_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 773
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(774): Parameter Declaration in module "stis_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 774
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(578): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 578
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(579): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 579
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(580): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 580
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(798): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 798
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(799): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 799
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(800): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 800
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10034): Output port "L_OUTp[1]" at stis_ana_demo.v(22) has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 22
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10034): Output port "L_OUTn[1]" at stis_ana_demo.v(22) has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 22
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(396): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 396
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(397): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 397
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(215): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 215
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(256): truncated value with size 32 to match size of target (7) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 256
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(258): truncated value with size 32 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 258
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(260): truncated value with size 16 to match size of target (10) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 260
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(263): truncated value with size 32 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 263
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(266): truncated value with size 16 to match size of target (7) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 266
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(269): truncated value with size 32 to match size of target (7) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 269
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(272): truncated value with size 32 to match size of target (7) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 272
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(274): truncated value with size 16 to match size of target (7) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 274
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(279): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 279
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(281): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 281
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(414): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 414
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(421): truncated value with size 22 to match size of target (9) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 421
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(427): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 427
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(435): truncated value with size 32 to match size of target (2) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 435
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(438): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 438
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(447): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 447
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(27): truncated value with size 32 to match size of target (5) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 27
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(47): truncated value with size 32 to match size of target (5) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 47
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(640): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 640
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(743): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 743
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(634): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 634
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(655): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 655
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(666): truncated value with size 32 to match size of target (12) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 666
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(686): truncated value with size 32 to match size of target (12) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 686
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(712): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 712
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(379): truncated value with size 32 to match size of target (12) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 379
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(404): truncated value with size 32 to match size of target (8) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 404
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10036): Verilog HDL or VHDL warning at dorn.v(566): object "adc_valid" assigned a value but never read File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 566
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(594): truncated value with size 32 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 594
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(599): truncated value with size 4 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 599
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(626): truncated value with size 32 to match size of target (5) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 626
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(631): truncated value with size 32 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 631
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(638): truncated value with size 5 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 638
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(643): truncated value with size 6 to match size of target (5) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 643
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(655): truncated value with size 32 to match size of target (2) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 655
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(706): truncated value with size 13 to match size of target (12) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 706
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(75): truncated value with size 32 to match size of target (2) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 75
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(163): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 163
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(871): truncated value with size 32 to match size of target (14) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 871
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(893): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 893
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(907): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 907
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(911): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 911
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(936): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 936
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(947): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 947
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(949): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 949
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(971): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 971
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(981): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 981
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(982): truncated value with size 32 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 982
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(1009): truncated value with size 32 to match size of target (26) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1009
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(499): truncated value with size 32 to match size of target (12) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 499
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(504): truncated value with size 24 to match size of target (12) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 504
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(504): truncated value with size 48 to match size of target (12) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 504
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(504): truncated value with size 96 to match size of target (12) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 504
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(504): truncated value with size 192 to match size of target (12) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 504
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(1118): truncated value with size 32 to match size of target (2) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1118
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(1132): truncated value with size 32 to match size of target (2) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1132
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(38): truncated value with size 26 to match size of target (25) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 38
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(39): truncated value with size 26 to match size of target (25) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 39
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(40): truncated value with size 32 to match size of target (15) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 40
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(55): truncated value with size 26 to match size of target (25) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 55
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(57): truncated value with size 26 to match size of target (25) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 57
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(83): truncated value with size 32 to match size of target (15) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 83
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(85): truncated value with size 16 to match size of target (15) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 85
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(86): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 86
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(91): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/divider.v Line: 91
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(1213): truncated value with size 32 to match size of target (7) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/dorn.v Line: 1213
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at log7to4.v(33): truncated value with size 32 to match size of target (5) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/l3/log7to4.v Line: 33
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at log7to4.v(36): truncated value with size 40 to match size of target (7) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/l3/log7to4.v Line: 36
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/packetfifo.v Line: 70
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(151): truncated value with size 32 to match size of target (10) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/packetfifo.v Line: 151
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(172): truncated value with size 32 to match size of target (10) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/packetfifo.v Line: 172
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (5) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/countbits.v Line: 13
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (10) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/countbits.v Line: 13
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(640): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 640
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(743): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 743
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(634): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 634
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(655): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 655
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(666): truncated value with size 32 to match size of target (12) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 666
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(686): truncated value with size 32 to match size of target (12) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 686
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(712): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_core.v Line: 712
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(461): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 461
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(462): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 462
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(468): truncated value with size 32 to match size of target (2) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 468
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(1622): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 1622
|
||
|
|
quartus/stis_ana_demo_c10.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(1645): truncated value with size 32 to match size of target (2) File: /home/blaulicht/stephan/svn@asterix/solo/eda/sirena/altera/memport.v Line: 1645
|
||
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quartus/stis_ana_demo_c10.map.rpt:Warning (12241): 8 hierarchies have connectivity warnings - see the Connectivity Checks report folder
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quartus/stis_ana_demo_c10.map.rpt:Warning (13034): The following nodes have both tri-state and non-tri-state drivers
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quartus/stis_ana_demo_c10.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AA[15]" and its non-tri-state driver. File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 13
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quartus/stis_ana_demo_c10.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AA[14]" and its non-tri-state driver. File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 13
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quartus/stis_ana_demo_c10.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AA[9]" and its non-tri-state driver. File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 13
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quartus/stis_ana_demo_c10.map.rpt:Warning (13039): The following bidirectional pins have no drivers
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quartus/stis_ana_demo_c10.map.rpt: Warning (13040): bidirectional pin "AA[13]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 13
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quartus/stis_ana_demo_c10.map.rpt: Warning (13040): bidirectional pin "AA[12]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 13
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quartus/stis_ana_demo_c10.map.rpt: Warning (13040): bidirectional pin "AA[11]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 13
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quartus/stis_ana_demo_c10.map.rpt: Warning (13040): bidirectional pin "AA[10]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 13
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quartus/stis_ana_demo_c10.map.rpt: Warning (13040): bidirectional pin "AA[8]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 13
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quartus/stis_ana_demo_c10.map.rpt: Warning (13040): bidirectional pin "AA[7]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 13
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quartus/stis_ana_demo_c10.map.rpt: Warning (13040): bidirectional pin "AA[6]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 13
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quartus/stis_ana_demo_c10.map.rpt: Warning (13040): bidirectional pin "AA[5]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 13
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quartus/stis_ana_demo_c10.map.rpt: Warning (13040): bidirectional pin "debug[3]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 34
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quartus/stis_ana_demo_c10.map.rpt: Warning (13040): bidirectional pin "debug[2]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 34
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quartus/stis_ana_demo_c10.map.rpt: Warning (13040): bidirectional pin "debug[1]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 34
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quartus/stis_ana_demo_c10.map.rpt:Warning (13009): TRI or OPNDRN buffers permanently enabled
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quartus/stis_ana_demo_c10.map.rpt: Warning (13010): Node "AA[15]~synth" File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 13
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||
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quartus/stis_ana_demo_c10.map.rpt: Warning (13010): Node "AA[14]~synth" File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 13
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||
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quartus/stis_ana_demo_c10.map.rpt: Warning (13010): Node "AA[9]~synth" File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 13
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quartus/stis_ana_demo_c10.map.rpt:Warning (13024): Output pins are stuck at VCC or GND
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quartus/stis_ana_demo_c10.map.rpt: Warning (13410): Pin "L_OUTp[1]" is stuck at GND File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 22
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quartus/stis_ana_demo_c10.map.rpt: Warning (13410): Pin "L_OUTn[1]" is stuck at GND File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 22
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||
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quartus/stis_ana_demo_c10.map.rpt: Warning (13410): Pin "A[19]" is stuck at GND File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 30
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||
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quartus/stis_ana_demo_c10.map.rpt: Warning (13410): Pin "A[20]" is stuck at GND File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 30
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||
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quartus/stis_ana_demo_c10.map.rpt:Warning (21074): Design contains 2 input pin(s) that do not drive logic
|
||
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quartus/stis_ana_demo_c10.map.rpt: Warning (15610): No output dependent on input pin "L_IN[4]" File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 23
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quartus/stis_ana_demo_c10.map.rpt: Warning (15610): No output dependent on input pin "L_IN[1]" File: /home/blaulicht/stephan/svn@asterix/solo/eda/dorn/altera/stis_ana_demo.v Line: 23
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||
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quartus/stis_ana_demo_c10.map.rpt:Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 229 warnings
|
||
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quartus/stis_ana_demo_c10.sta.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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||
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quartus/stis_ana_demo_c10.sta.rpt:Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
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