quartus/erena.asm.rpt:Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
quartus/erena.fit.rpt: 5. I/O Assignment Warnings
quartus/erena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
quartus/erena.fit.rpt:; I/O Assignment Warnings ;
quartus/erena.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/erena.fit.rpt:Warning (15536): Implemented PLL "pll240:pll0|altpll:altpll_component|altpll_2143:auto_generated|pll1" as Cyclone III PLL type, but with warnings
quartus/erena.fit.rpt: Warning (15559): Can't achieve requested value 57.6 degrees for clock output pll240:pll0|altpll:altpll_component|altpll_2143:auto_generated|clk[1] of parameter phase shift -- achieved value of 60.0 degrees
quartus/erena.fit.rpt: Warning (15559): Can't achieve requested value 86.4 degrees for clock output pll240:pll0|altpll:altpll_component|altpll_2143:auto_generated|clk[3] of parameter phase shift -- achieved value of 90.0 degrees
quartus/erena.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
quartus/erena.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
quartus/erena.fit.rpt:Warning (176674): Following 8 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
quartus/erena.fit.rpt: Warning (176118): Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
quartus/erena.fit.rpt: Warning (176118): Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
quartus/erena.fit.rpt: Warning (176118): Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
quartus/erena.fit.rpt: Warning (176118): Pin "adc_clk[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "adc_clk[2](n)"
quartus/erena.fit.rpt: Warning (176118): Pin "adc_clk[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "adc_clk[1](n)"
quartus/erena.fit.rpt: Warning (176118): Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
quartus/erena.fit.rpt: Warning (176118): Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
quartus/erena.fit.rpt: Warning (176118): Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
quartus/erena.fit.rpt:Warning (176225): Can't pack node adc_data2:ad1|ndin[11] to I/O pin
quartus/erena.fit.rpt: Warning (176228): Can't pack node adc_data2:ad1|ddin[1][11] and I/O node adc_da1[11] -- I/O node is a dedicated I/O pin
quartus/erena.fit.rpt: Warning (176228): Can't pack node adc_data2:ad1|ndin[11] and I/O node adc_da1[11] -- I/O node is a dedicated I/O pin
quartus/erena.fit.rpt:Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/erena.fit.rpt:Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/erena.fit.rpt:Info: Quartus II 32-bit Fitter was successful. 0 errors, 26 warnings
quartus/erena.map.rpt:; old ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/erena.map.rpt:; old ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/erena.map.rpt:; trouble ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/erena.map.rpt:; halffull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/erena.map.rpt:; fifo_empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/erena.map.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/erena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ms5540c.v(120): Parameter Declaration in module "ms5540c" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/erena.map.rpt:Warning (10030): Net "fifo[4]" at erena.v(101) has no driver or initial value, using a default initial value '0'
quartus/erena.map.rpt:Warning (10030): Net "fsiz[4]" at erena.v(101) has no driver or initial value, using a default initial value '0'
quartus/erena.map.rpt:Warning (10030): Net "fhma[4]" at erena.v(101) has no driver or initial value, using a default initial value '0'
quartus/erena.map.rpt:Warning (10030): Net "fhva[4]" at erena.v(101) has no driver or initial value, using a default initial value '0'
quartus/erena.map.rpt:Warning (10296): VHDL warning at pll240.vhd(194): ignored assignment of value to null range
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(254): truncated value with size 32 to match size of target (8)
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(256): truncated value with size 32 to match size of target (8)
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3)
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(150): truncated value with size 32 to match size of target (10)
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(171): truncated value with size 32 to match size of target (10)
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (5)
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (10)
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_master_adc.v(99): truncated value with size 32 to match size of target (4)
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at epipe.v(247): truncated value with size 32 to match size of target (9)
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at epipe.v(117): truncated value with size 21 to match size of target (18)
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at epipe.v(453): truncated value with size 32 to match size of target (8)
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at epipe.v(374): truncated value with size 32 to match size of target (4)
quartus/erena.map.rpt:Warning (10230): Verilog HDL assignment warning at epipe.v(396): truncated value with size 25 to match size of target (11)
quartus/erena.map.rpt:Warning (12241): 5 hierarchies have connectivity warnings - see the Connectivity Checks report folder
quartus/erena.map.rpt:Warning (13024): Output pins are stuck at VCC or GND
quartus/erena.map.rpt: Warning (13410): Pin "adc_sync[2]" is stuck at GND
quartus/erena.map.rpt: Warning (13410): Pin "adc_sync[1]" is stuck at GND
quartus/erena.map.rpt:Warning (15899): PLL "pll240:pll0|altpll:altpll_component|altpll_2143:auto_generated|pll1" has parameters clk2_multiply_by and clk2_divide_by specified but port CLK[2] is not connected
