solo_altera/irena/altera/irena.warnings

irena.asm.rpt:Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
irena.fit.rpt:  5. I/O Assignment Warnings
irena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
irena.fit.rpt:; I/O Assignment Warnings                             ;
irena.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
irena.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
irena.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
irena.fit.rpt:Warning (176674): Following 6 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
irena.fit.rpt:    Warning (176118): Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
irena.fit.rpt:    Warning (176118): Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
irena.fit.rpt:    Warning (176118): Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
irena.fit.rpt:    Warning (176118): Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
irena.fit.rpt:    Warning (176118): Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
irena.fit.rpt:    Warning (176118): Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
irena.fit.rpt:Warning (176225): Can't pack node direna:core|a_data[8] to I/O pin
irena.fit.rpt:    Warning (176228): Can't pack node direna:core|a_data[8] and I/O node adc_sdata[8] -- I/O node is a dedicated I/O pin
irena.fit.rpt:Warning (176225): Can't pack node direna:core|a_data[10] to I/O pin
irena.fit.rpt:    Warning (176228): Can't pack node direna:core|a_data[10] and I/O node adc_sdata[10] -- I/O node is a dedicated I/O pin
irena.fit.rpt:Warning (176225): Can't pack node direna:core|a_data[9] to I/O pin
irena.fit.rpt:    Warning (176228): Can't pack node direna:core|a_data[9] and I/O node adc_sdata[9] -- I/O node is a dedicated I/O pin
irena.fit.rpt:Warning (169180): Following 18 pins must use external clamping diodes.
irena.fit.rpt:Info: Quartus II 32-bit Fitter was successful. 0 errors, 17 warnings
irena.map.rpt:; halffull ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
irena.map.rpt:; maxT       ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (4 bits) it drives.  The 28 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
irena.map.rpt:; c1   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
irena.map.rpt:; c2   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
irena.map.rpt:; c3   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
irena.map.rpt:; c4   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
irena.map.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
irena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at adccntl.v(140): Parameter Declaration in module "adc_channels" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
irena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at irena.v(47): object "global_enable" assigned a value but never read
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at irena.v(64): truncated value with size 32 to match size of target (7)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at irena.v(75): truncated value with size 32 to match size of target (16)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at irena.v(76): truncated value with size 32 to match size of target (16)
irena.map.rpt:Warning (10034): Output port "debug" at irena.v(21) has no driver
irena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at adccntl.v(116): object "phmm" assigned a value but never read
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at adccntl.v(118): truncated value with size 32 to match size of target (20)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at trigger.v(127): truncated value with size 32 to match size of target (5)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at trigger.v(159): truncated value with size 32 to match size of target (5)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at trigger.v(165): truncated value with size 32 to match size of target (5)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(253): truncated value with size 32 to match size of target (8)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(255): truncated value with size 32 to match size of target (8)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(141): truncated value with size 32 to match size of target (10)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(162): truncated value with size 32 to match size of target (10)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(12): truncated value with size 32 to match size of target (10)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(124): truncated value with size 32 to match size of target (11)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(126): truncated value with size 32 to match size of target (11)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(145): truncated value with size 32 to match size of target (8)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(193): truncated value with size 32 to match size of target (5)
irena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(12): truncated value with size 32 to match size of target (16)
irena.map.rpt:Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
irena.map.rpt:Warning (13024): Output pins are stuck at VCC or GND
irena.map.rpt:    Warning (13410): Pin "debug[6]" is stuck at GND
irena.map.rpt:    Warning (13410): Pin "debug[5]" is stuck at GND
irena.map.rpt:Warning (15899): PLL "pll96:pll0|altpll:altpll_component|altpll_pn43:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
irena.map.rpt:Warning (21074): Design contains 2 input pin(s) that do not drive logic
irena.map.rpt:    Warning (15610): No output dependent on input pin "clk_T1"
irena.map.rpt:    Warning (15610): No output dependent on input pin "trigger"
irena.map.rpt:Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 33 warnings
irena.sta.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
irena.sta.rpt:Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning