solo_altera/pirena/altera/Makefile

PROJ=pirena

VERILOG=/usr/local/bin/iverilog
#VERILOG=/usr/bin/iverilog

VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
%.vvp: %.v
	$(VERILOG) $(VERILOGFLAGS) -o $@ $^

vcd/%.lxt: %.vvp
	$< -lxt2 | tee $*.log

.PRECIOUS: vcd/%.lxt

VPATH=.:./direna:../../altera:../../altera/mega:../../nm64/altera

$(PROJ)_FLAGS = -D$(PROJ)_TEST -s $(PROJ)_test
pirena.vvp: $(PROJ)_test.v frontend.v spi_slave.v spififo_sim.v \
             conf_reg.v packetfifo.v trigen.v countbits.v \
             ad7690.v frontend_test.v ltc2656.v

QUARTUS=/usr/local/quartus/altera13.1/quartus
export PATH:=$(PATH):$(QUARTUS)/bin

MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS))

QDIR=quartus

$(QDIR)/%.rbf: %.qpf %.qsf %.sdc \
       frontend.v spi_slave.v conf_reg.v packetfifo.v spififo.v countbits.v 
	quartus_map $< $(MAPFLGS)
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning $(QDIR)/$*.*.rpt > $*.warnings

ADC_SAMPLE_EARLY = ADC_SAMPLE_EARLY=1
pirena_MAPDEFS = $(no_ADC_SAMPLE_EARLY) 

$(QDIR)/pirena.rbf: pirena.v ad7690.v trigen.v pll96.v ltc2656.v