solo_altera/stein/altera/Makefile

# need iverilog version 0.10 for signed integers
# VERILOG=/usr/local/bin/iverilog
VERILOG=iverilog

VERILOGFLAGS = -v -Wall -Wno-timescale -DSIMULATION $(IVLFLAGS) $($*_FLAGS)
%.vvp:
	$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v, $^)

lxt/%.lxt: %.vvp
	mkdir -p lxt/
	$< -lxt2 | tee $*.log

.PRECIOUS: lxt/%.lxt

VPATH=../../irena/altera/adc128:../../altera:../../altera/mega:../../idef-x/altera:\
../../altera/actel:../../sirena/altera:../../sirena/altera/l3:\
../../sirena/altera/encode:../../hetept/altera:\
../../arena/altera/idef-x:../../arena/altera

stein.vvp: stein.v stein_core.v stein_pha.v frontend.v backend.v memport.v \
   message.v uart.v l3code.v crc.v msg_regs.v \
   mem.v fifo.v hamming.v counters.v \
   ppsschedule.v pha.v eeprom.v l3registerfile.v \
   processor.v l3regfifo.v adder.v adderi.v mult.v log7to4.v trim.v bitrange.v cmp.v \
   compression.v encode.v itof.v log2by8.v \
   opheater.v sfilter.v \
   stein_middleend.v stein_frontend.v clk_domain_switch.v stein_ix_controller.v stein_l1_counter.v stein_l2trig.v \
   stein_adc_controller.v leadingbit.v stein_ix_acquire_switch.v countbits.v stein_channel_map.v \
   barrel.v priority_encoder.v adc128s102.v idefx.v \
   serializer.v \
   ix.v testpulser.v

stein_FLAGS = -sstein_test -DSTEIN_TEST -DUART3MHZ -DINFERRED_SRAM -DM24MHZ -DTRIG_NOINVERT

step.vvp: step.v stein_core.v stein_pha.v frontend.v backend.v memport.v por.v \
   message.v uart.v l3code.v crc.v msg_regs.v \
   mem.v fifo.v hamming.v counters.v \
   ppsschedule.v pha.v eeprom.v l3registerfile.v \
   processor.v l3regfifo.v adder.v adderi.v mult.v log7to4.v trim.v bitrange.v cmp.v \
   compression.v encode.v itof.v log2by8.v \
   opheater.v sfilter.v \
   stein_channel_map.v \
   stein_middleend.v stein_frontend.v clk_domain_switch.v stein_ix_controller.v stein_l1_counter.v stein_l2trig.v \
   stein_adc_controller.v leadingbit.v stein_ix_acquire_switch.v countbits.v \
   barrel.v priority_encoder.v adc128s102.v idefx.v \
   serializer.v \
   ix.v testpulser.v actel.v

step_FLAGS = -sstep_test -DSTEP_TEST -DUART3MHZ -DINFERRED_SRAM -DM24MHZ -DTRIG_NOINVERT -DARxSTREAM

l3win_test.vvp: step_l3win_test.v stein_pha.v backend.v hamming.v \
	l3code.v l3registerfile.v ppsschedule.v memport.v fifo.v \
	message.v pha.v eeprom.v msg_regs.v counters.v mem.v \
        compression.v encode.v itof.v log2by8.v \
	processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v adderi.v mult.v bitrange.v \
	step.l3v step_dps.iv stein_channel_map.v countbits.v

l3win_test_FLAGS = -sl3win_test -DL3WIN_TEST -DUART3MHZ -DINFERRED_SRAM -DM24MHZ -DTRIG_NOINVERT -DARxSTREAM

QUARTUS=/usr/local/quartus/altera9.1sp1/quartus
export PATH:=$(PATH):$(QUARTUS)/bin

MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS))

%.rbf: %.qpf %.qsf %.sdc %.v 
	quartus_map $< $(MAPFLGS)
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning $*.*.rpt \
      | grep -v 'truncated value with size 32 to match size of target' \
      | grep -v 'behaves as a Local Parameter Declaration because the module has a Module Parameter Port List' \
      > $*.warnings

stein.rbf: pll96.v stein.v stein_core.v stein_pha.v stein_channel_map.v \
 stein_frontend.v stein_middleend.v \
 stein_ix_controller.v clk_domain_switch.v stein_l1_counter.v stein_l2trig.v \
 stein_adc_controller.v leadingbit.v countbits.v stein_ix_acquire_switch.v \
 barrel.v priority_encoder.v adc128s102.v \
 memport.v backend.v message.v uart.v por.v ix.v testpulser.v \
 l3code.v crc.v msg_regs.v fifo.v hamming.v mem.v \
 counters.v ppsschedule.v pha.v eeprom.v l3registerfile.v \
 l3/processor.v l3/l3regfifo.v l3/adder.v l3/adderi.v l3/mult.v \
 l3/log7to4.v l3/trim.v  l3/bitrange.v l3/cmp.v \
 encode/compression.v encode/encode.v itof.v log2by8.v opheater.v sfilter.v \

stein_test.rbf: pll96.v stein.v stein_core.v stein_pha.v \
 stein_frontend.v stein_middleend.v \
 memport.v backend.v message.v uart.v \
 l3code.v crc.v msg_regs.v fifo.v hamming.v mem.v \
 counters.v ppsschedule.v pha.v eeprom.v l3registerfile.v \
 l3/processor.v l3/l3regfifo.v l3/adder.v l3/adderi.v l3/mult.v \
 l3/log7to4.v l3/trim.v  l3/bitrange.v l3/cmp.v \
 encode/compression.v encode/encode.v itof.v sfilter.v \
 clk_domain_switch.v stein_ix_controller.v stein_l1_counter.v stein_l2trig.v \
 stein_adc_controller.v leadingbit.v stein_ix_acquire_switch.v countbits.v \
 barrel.v priority_encoder.v
	rm -f stein.rbf
	$(MAKE) stein_MAPDEFS=TRIG_NOINVERT=1 stein.rbf
	mv stein.rbf $@
	mv stein.warnings stein_test.warnings

stein_ix_controller_acquire.vvp: stein_ix_controller.v stein_adc_controller.v stein_l2trig.v countbits.v memWxActel.v RAM64K36_sim.v mem36x128.v mem.v hamming.v sfilter.v barrel.v priority_encoder.v adc128s102.v idefx.v ix.v stein_channel_map.v
stein_ix_controller_acquire_FLAGS = -DIX_ACQUIRE_TEST -DTARGET_ACTEL -six_acquire_test -DARxSTREAM

stein_adc_controller.vvp: stein_adc_controller.v barrel.v priority_encoder.v adc128s102.v
stein_adc_controller_FLAGS = -DSTEIN_ADC_CONTROLLER_TEST -sstein_adc_controller_test

stein_ix_controller_temp.vvp: stein_ix_controller.v stein_adc_controller.v sfilter.v barrel.v priority_encoder.v adc128s102.v
stein_ix_controller_temp_FLAGS = -DIX_TEMP_TEST -six_temp_test

stein_ix_controller_sc.vvp: stein_ix_controller.v leadingbit.v idefx.v ix.v
stein_ix_controller_sc_FLAGS = -DIX_SC_SCHEDULER_TEST -six_sc_scheduler_test

stein_hk.vvp: stein_core.v stein_pha.v stein_ix_controller.v stein_adc_controller.v sfilter.v barrel.v priority_encoder.v countbits.v adc128s102.v
stein_hk_FLAGS = -DSTEIN_HK_TEST -sstein_hk_test

stein_ix_controller_reset.vvp: stein_ix_controller.v
stein_ix_controller_reset_FLAGS = -DIX_RESET_TEST -six_reset_test

stein_ix_acquire_switch.vvp: stein_ix_acquire_switch.v stein_ix_controller.v stein_adc_controller.v stein_l2trig.v countbits.v memWxActel.v RAM64K36_sim.v mem36x128.v mem.v hamming.v sfilter.v barrel.v priority_encoder.v clk_domain_switch.v adc128s102.v
stein_ix_acquire_switch_FLAGS = -DIX_ACQUIRE_SWITCH_TEST -DINFERRED_SRAM -DM24MHZ -six_acquire_switch_test

clk_domain_switch.vvp: clk_domain_switch.v
clk_domain_switch_FLAGS = -DCLK_DOMAIN_SWITCH_TEST -DM24MHZ -sclk_domain_switch_test

stein_frontend.vvp: stein_frontend.v stein_adc_controller.v stein_ix_controller.v adc128s102.v barrel.v priority_encoder.v stein_l1_counter.v stein_l2trig.v counters.v countbits.v leadingbit.v idefx.v
stein_frontend_FLAGS = -DSTEIN_FRONTEND_TEST -sstein_frontend_test

idefx.vvp: idefx.v
idefx_FLAGS = -DIDEFX_TEST -sidefx_test

stein_l2trig.vvp: stein_l2trig.v countbits.v
stein_l2trig_FLAGS = -DSTEIN_L2TRIG_TEST -sstein_l2trig_test

stein_middleend.vvp: stein_middleend.v stein_ix_controller.v stein_l1_counter.v countbits.v leadingbit.v idefx.v counters.v
stein_middleend_FLAGS = -DSTEIN_MIDDLEEND_TEST -sstein_middleend_test

stein_sc_write.vvp: stein_core.v stein_pha.v
stein_sc_write_FLAGS = -DSC_WRITE_TEST -ssc_write_test

stein_package_maker.vvp: stein_pha.v stein_ix_acquire_switch.v stein_ix_controller.v stein_adc_controller.v stein_l2trig.v countbits.v memWxActel.v RAM64K36_sim.v mem36x128.v mem.v hamming.v sfilter.v barrel.v priority_encoder.v clk_domain_switch.v adc128s102.v
stein_package_maker_FLAGS = -DSTEIN_PACKAGE_MAKER_TEST -DINFERRED_SRAM -DM24MHZ -sstein_package_maker_test

i14tof11.vvp: stein_core.v
i14tof11_FLAGS = -DI14TOF11_TEST -si14tof11_test

%.l3v: %.l3
	$(MAKE) -C ../../sirena/altera ../../stein/altera/$@