split out timecode bits
fix ready/error LED color
connect port 2 TC LEDs
fix port 2 fifo3 hval
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7095 bc5caf13-1734-44f8-af43-603852e9ee25
add core2, feeding fifo3
core feeds fifos 1 and 2
clk384 replaced bu 192MHz fclk, altera cannot do an 17 bit adder at 384MHz
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5864 bc5caf13-1734-44f8-af43-603852e9ee25