Commit graph

8 commits

Author SHA1 Message Date
stephan
dba49942ad spwirena: fix timestamp
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7134 bc5caf13-1734-44f8-af43-603852e9ee25
2018-11-28 23:00:28 +00:00
stephan
889e95f811 spwirena: misc fixes
split out timecode bits
	fix ready/error LED color
	connect port 2 TC LEDs
	fix port 2 fifo3 hval


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7095 bc5caf13-1734-44f8-af43-603852e9ee25
2018-11-15 10:12:06 +00:00
stephan
9fdaa2c17a spwirena: 2-color LEDs
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5950 bc5caf13-1734-44f8-af43-603852e9ee25
2017-03-15 23:01:11 +00:00
stephan
97f30a8dea spwirena: fix RxD timings, blinkenlights, ready--running
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5873 bc5caf13-1734-44f8-af43-603852e9ee25
2017-02-20 20:10:28 +00:00
stephan
de3620f55c spwirena: moved clock_buffer to serializer.v
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5871 bc5caf13-1734-44f8-af43-603852e9ee25
2017-02-20 07:59:55 +00:00
stephan
2456cd74fd spwirena: core2, altera
add core2, feeding fifo3
	core feeds fifos 1 and 2
	clk384 replaced bu 192MHz fclk, altera cannot do an 17 bit adder at 384MHz



git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5864 bc5caf13-1734-44f8-af43-603852e9ee25
2017-02-17 20:04:49 +00:00
stephan
13742c4e0e swirena: fixes and core2(disbaled)
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5860 bc5caf13-1734-44f8-af43-603852e9ee25
2017-02-17 13:14:46 +00:00
stephan
19d7d77581 spwirena: altera template
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5854 bc5caf13-1734-44f8-af43-603852e9ee25
2017-02-15 23:48:56 +00:00