stephan
a007e5cfbe
nmleia_c3: pinout for nmrena_v1 board
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9395 bc5caf13-1734-44f8-af43-603852e9ee25
2025-11-05 19:55:31 +00:00
stephan
060d928727
altera/pll192: 10LC mega wizard
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The wizzard offers two output modes, for defining the
clk parameters.
pll192h.v: high level muliplier, divider and phase in ps
pll192l.v: PLL m/n and counter taps for the clk transitions.
Those two files should behave identically.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9113 bc5caf13-1734-44f8-af43-603852e9ee25
2024-09-17 19:46:34 +00:00
stephan
27c7972d5b
pll96: adjust phases, *edge .c4() shall align with negedge .c0()
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7980 bc5caf13-1734-44f8-af43-603852e9ee25
2020-03-12 23:54:10 +00:00
stephan
b355a39bf7
pll96: 16, 32, 48, 64, 96 MHz
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7943 bc5caf13-1734-44f8-af43-603852e9ee25
2020-03-01 22:52:50 +00:00
stephan
5af870a7b8
nm_mcs: sim and synthesis
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7918 bc5caf13-1734-44f8-af43-603852e9ee25
2020-02-18 04:46:31 +00:00
stephan
500bf34ac9
new nmrena usage: nm_mcs
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7916 bc5caf13-1734-44f8-af43-603852e9ee25
2020-02-17 19:32:23 +00:00
stephan
63b087b112
nmrena: uart implementation, just typed in, no testing
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@6201 bc5caf13-1734-44f8-af43-603852e9ee25
2017-08-22 22:39:15 +00:00
stephan
6dd01df1c0
spififo: add parameter ALMOST
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5863 bc5caf13-1734-44f8-af43-603852e9ee25
2017-02-17 19:57:36 +00:00
stephan
47789acefd
mega: lvds io buffer
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5688 bc5caf13-1734-44f8-af43-603852e9ee25
2016-11-30 13:21:35 +00:00
stephan
289256cea9
altera: PLL base clock recovery failed, use 4x oversampling at 384 MHz
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2412 bc5caf13-1734-44f8-af43-603852e9ee25
2013-12-17 12:02:32 +00:00
stephan
8c24c80db1
serializer: clock recovery PLL
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2236 bc5caf13-1734-44f8-af43-603852e9ee25
2013-10-15 16:49:09 +00:00
stephan
a9953050eb
backend in flyrena fits inside cyclon 3c25
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1432 bc5caf13-1734-44f8-af43-603852e9ee25
2013-01-03 00:44:07 +00:00
stephan
9b87e83be7
fast adc_data sampling, adc diff mode
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1273 bc5caf13-1734-44f8-af43-603852e9ee25
2012-08-25 12:32:07 +00:00
stephan
d5515f46e6
fix flyrena synthesis
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1236 bc5caf13-1734-44f8-af43-603852e9ee25
2012-08-06 18:21:28 +00:00
stephan
d2cbd614fb
ADCtest with sfilter
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@949 bc5caf13-1734-44f8-af43-603852e9ee25
2012-02-21 15:30:45 +00:00
stephan
759c26b04f
add pll240(d) VHDL files
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@753 bc5caf13-1734-44f8-af43-603852e9ee25
2011-11-28 22:07:37 +00:00
stephan
9698d215a0
modified copy of sram1024x32.v
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@575 bc5caf13-1734-44f8-af43-603852e9ee25
2011-08-15 07:33:47 +00:00
stephan
62c8e3ca2b
Move megafunction to new library directory
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git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@464 bc5caf13-1734-44f8-af43-603852e9ee25
2011-05-17 06:30:20 +00:00
