Increase memory dump size counter to 16-bit.
Add output exec to l3dump, signaling reads when msg_da[48] was set.
Add backend output exec, exec_da[7:0] for EERPOM reads.
TODO: implement a message generator. Read 12 bytes per message, that is
enough delay between messages.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5175 bc5caf13-1734-44f8-af43-603852e9ee25
We were loosing data items in the science packets.
The go_wim and go_enc counters differed, there were go_enc missing.
Hypothesis: win_sum_valid were dropped under memory bus load.
Code review: a memport val shall never be qualified by conditions
unless you can make absolutely sure you get exactly all the val you need.
This patch reimplements memwindow.valid and memwindow.busy
so that we always get a valid after a go, and the busy is long enough
to prevent the dps to gobble up a window to fast.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4421 bc5caf13-1734-44f8-af43-603852e9ee25
This command clears all registers to zero.
The register prefetch pipeline will fetch uninitialized
registers which cause repeated EDAC errors.
We may do away with the Z register @R[0]. Z=0xdf instead?
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4355 bc5caf13-1734-44f8-af43-603852e9ee25
por is treated as abort
por resets the opheater
There is a 1 in 256 chance that the por will not happen
if registers initialize randomly at power on.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4152 bc5caf13-1734-44f8-af43-603852e9ee25
Reorganization of reset/abort/atbrk.
Argument size warnings.
Preparation for iverilog 0.10 (git)
Icarus verilog version 0.10 issues warnings for unsized (0)
connected to single ports. These were fixed.
Version 0.10 (git of today) does time 0 initializations
differently. The tfifo used to get reset a time 0, not any
more. A simple reset issued to message() did not succeed,
because undefined state from the tfifo trickles through the tport
chain, to set the message module back to undefined. This was
fixed by wireing abort into tports.
errors[4] = atbrk is fixed. It was always triggering itself
via strobes[0]. Now it really just triggers by the atbrk
sequence.
Gold for step, flyrena, heteptdig.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3978 bc5caf13-1734-44f8-af43-603852e9ee25
wire TxE to ~confs[5:4], invert EEPROM_nRES
Both LDVS drivers and the EEPROM are enabled when confs==0.
Now we can disable the unused LVDS driver.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3904 bc5caf13-1734-44f8-af43-603852e9ee25
The flight EEPROM requires at least 750ns between nWE pulses.
The memory driver gives 80ns. The consequence is that we were
not able to write to the HET/EPT PQM EEPROM.
This change add delays in the eeprom_page engine to ensure sufficient
time between write cycles.
A write is started after two uticks passed. That yields 2µs per byte
under non-contetsted memory bus conditions. This also provides lower
priority access slots during an EEPROM page write.
The maximum time between write cycles must be no more than 30µs,
else the EEPROM will start commiting the page to persistent
flash cells.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3805 bc5caf13-1734-44f8-af43-603852e9ee25
Use only one RAM block for pha_acc_mem.
The SUE of the removed RAM block causes different PRNG sequences
for the analog input data.
Also: pass -v to vvp.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3593 bc5caf13-1734-44f8-af43-603852e9ee25
Use separate memory in pha_acc_mem for tcnt and wptr.
This allows for 24 bit tcnt without an extra RAM block.
The extra RAM block is still there, not to mess up the PRNG.
The next commit will have the extra RAM removed and a
new gold file.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3592 bc5caf13-1734-44f8-af43-603852e9ee25
New reset: e_reset = strobes[6]
Restore orthogonal meanings to
e_enable, l3_enable, pha_enable.
Do not clear events at ~e_enable. Events will be processed
when ~e_enable. Do not clear events at ~l3_enable. Events can
be stored without processing them immediately.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3554 bc5caf13-1734-44f8-af43-603852e9ee25
Provide a confs port all the way to the toplevel.
Use confs[7] to drive EEPROM_nRES.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3507 bc5caf13-1734-44f8-af43-603852e9ee25
A change in module aschedule for STEP broke heteptana hkadc.
The change suppressed din1 and doute strobes when the ADC is not active.
This had two effects:
1. The hkadc state machine would hang at startup.
2. The state machine would not terminate reading the sequence.
This was fixed by driving the state from mtick, and fix the resulting
timing shifts. The result is a more robust design of the hkadc module.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3505 bc5caf13-1734-44f8-af43-603852e9ee25
When this macro is defined, the B-channel data from the filter
is ignored, and zeros used instead. The effect is that close to
half the logic will optimize out. Let's try.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3392 bc5caf13-1734-44f8-af43-603852e9ee25
Remove `ifdef TARGET_ACTEL from FPGA toplevel modules.
Provide models for the Actel buffers in use.
This version now properly models the interconnection
of the FPGAs.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3390 bc5caf13-1734-44f8-af43-603852e9ee25
Add ARxDD register in the IO-pad.
Add a mergable register in sermerge, to share with
the deserializer, just in case.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3388 bc5caf13-1734-44f8-af43-603852e9ee25
Add a 8-bit port to feed status bits to the status register
all the way from the toplevel,
and used one bit for EEPROM_BUSY.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3387 bc5caf13-1734-44f8-af43-603852e9ee25
