The user of this port have been moved to spare cntrs to bank 0x40.
Debug counters in step_core where removed.
TODO: sirena
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4402 bc5caf13-1734-44f8-af43-603852e9ee25
por is treated as abort
por resets the opheater
There is a 1 in 256 chance that the por will not happen
if registers initialize randomly at power on.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4152 bc5caf13-1734-44f8-af43-603852e9ee25
Reorganization of reset/abort/atbrk.
Argument size warnings.
Preparation for iverilog 0.10 (git)
Icarus verilog version 0.10 issues warnings for unsized (0)
connected to single ports. These were fixed.
Version 0.10 (git of today) does time 0 initializations
differently. The tfifo used to get reset a time 0, not any
more. A simple reset issued to message() did not succeed,
because undefined state from the tfifo trickles through the tport
chain, to set the message module back to undefined. This was
fixed by wireing abort into tports.
errors[4] = atbrk is fixed. It was always triggering itself
via strobes[0]. Now it really just triggers by the atbrk
sequence.
Gold for step, flyrena, heteptdig.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3978 bc5caf13-1734-44f8-af43-603852e9ee25
wire TxE to ~confs[5:4], invert EEPROM_nRES
Both LDVS drivers and the EEPROM are enabled when confs==0.
Now we can disable the unused LVDS driver.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3904 bc5caf13-1734-44f8-af43-603852e9ee25
make the backend register readout engine static, i.e., no waiting.
add scratch register in the backend [reg 3]
add pps status for both ports
move OH status.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3869 bc5caf13-1734-44f8-af43-603852e9ee25
The flight EEPROM requires at least 750ns between nWE pulses.
The memory driver gives 80ns. The consequence is that we were
not able to write to the HET/EPT PQM EEPROM.
This change add delays in the eeprom_page engine to ensure sufficient
time between write cycles.
A write is started after two uticks passed. That yields 2µs per byte
under non-contetsted memory bus conditions. This also provides lower
priority access slots during an EEPROM page write.
The maximum time between write cycles must be no more than 30µs,
else the EEPROM will start commiting the page to persistent
flash cells.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3805 bc5caf13-1734-44f8-af43-603852e9ee25
Review power on reset.
Add initial statements for synthesis, in case the
target supports a define power on state.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3558 bc5caf13-1734-44f8-af43-603852e9ee25
Provide a confs port all the way to the toplevel.
Use confs[7] to drive EEPROM_nRES.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3507 bc5caf13-1734-44f8-af43-603852e9ee25
A change in module aschedule for STEP broke heteptana hkadc.
The change suppressed din1 and doute strobes when the ADC is not active.
This had two effects:
1. The hkadc state machine would hang at startup.
2. The state machine would not terminate reading the sequence.
This was fixed by driving the state from mtick, and fix the resulting
timing shifts. The result is a more robust design of the hkadc module.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3505 bc5caf13-1734-44f8-af43-603852e9ee25
When this macro is defined, the B-channel data from the filter
is ignored, and zeros used instead. The effect is that close to
half the logic will optimize out. Let's try.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3392 bc5caf13-1734-44f8-af43-603852e9ee25
