Stephan/solo_altera
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181 commits

Author SHA1 Message Date
stephan
b6f9464cd0 irenacore: shift B-channel mantissa by 2 bits up to gain resolution 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5591 bc5caf13-1734-44f8-af43-603852e9ee25
 2016-11-10 07:51:22 +00:00
stephan
3cc2d1264e heteptana: C'E4 interface 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5478 bc5caf13-1734-44f8-af43-603852e9ee25
 2016-10-04 06:29:14 +00:00
stephan
afc434a323 sfilter dout_pipe: gold 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5477 bc5caf13-1734-44f8-af43-603852e9ee25
 2016-10-03 10:20:23 +00:00
stephan
ce2cbb6561 sfilter dout_pipe: sample DCLK to find propper tick phase 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5476 bc5caf13-1734-44f8-af43-603852e9ee25
 2016-10-03 10:19:49 +00:00
stephan
a20f15a962 verilog: fix a few nonblocking assignment s 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3969 bc5caf13-1734-44f8-af43-603852e9ee25
 2015-03-17 23:58:36 +00:00
stephan
41d63828c2 heteptana: merge -c 3599,3602 from em/v04 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3603 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-10 20:09:43 +00:00
stephan
6382c652ec sfilter: forward inverted adc control outputs 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3300 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-10-17 17:30:40 +00:00
stephan
753923daef adc128 filter: 
support new FO parameter of the adcschedule module


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3287 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-10-16 16:43:33 +00:00
stephan
63e4ec9c56 sfilter.v: 
This patch adds a register at the DOUT/SDATA input, before it is
	distributed to four SRAM blocks.

	This is necessary to meet worst case timing requirements of the ADCs.
	The ADCs require 27ns propagation delay from SCLK to SDATA.  The FPGA 
	must ensure the roundtrip clk -> SCLK -> SDATA -> clk takes no more
	than 62.5ns.  The aim is to constrain synthesis such that the sum of the
	delay clk->SCLK plus setup time DOUT->clk is shorter than 25ns.

	Obviously, there should be a register in the input pads of DOUT/SDATA.

	All inwards bound timing output of the aschedule module needs to be
	delayed by one clk cycle to cover for the extra register, that's all.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3264 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-10-14 18:40:42 +00:00
stephan
65c7ce0fb6 irenacore: updated test 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3156 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-09-09 09:58:10 +00:00
stephan
382b469990 sfilter samples: merge -c 2973 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2981 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-06-02 21:09:24 +00:00
stephan
2a1e31ffeb sfilter samples: fix timestamp for (unused) case NC%4==3 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2962 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-05-31 18:59:20 +00:00
stephan
70ff726460 irena_core: fix dranbuf address separation 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2797 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-04-25 14:48:23 +00:00
stephan
85308fefb1 irena_core: fix dranbuf address separation 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2796 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-04-25 14:39:19 +00:00
stephan
eca75cc94f packetfifo: add match parameter for variable size packets 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2681 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-03-27 22:49:48 +00:00
stephan
43e866c58f irenacore: simulation: add support to packet parser 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2680 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-03-27 20:33:38 +00:00
stephan
53f0287772 irenacore: turn off pass-through logic for inferred RAMs 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2679 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-03-27 16:22:49 +00:00
stephan
1eaa10f913 irenacore: quartus warnings with pass-through-logic 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2678 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-03-27 16:12:30 +00:00
stephan
81530dcff3 irenacore: quartus setup 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2677 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-03-27 16:07:34 +00:00
stephan
342570b126 irena_core: simulates 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2673 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-03-26 23:55:13 +00:00
stephan
955a973423 irena: direnacore good for irenacore transition 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2670 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-03-26 21:32:47 +00:00
stephan
f8969a2201 irena: fix simulation bitrot for classic direna baseline 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2663 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-03-25 23:29:16 +00:00
stephan
b6cd5b5818 irena: implement option to use the new trigger 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2407 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-12-15 22:07:32 +00:00
stephan
e3ba719108 irena_core: fix ABT2F 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2296 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-11-10 22:16:24 +00:00
stephan
666bfd5a44 irena_core: use MSB of A,B in peek 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2289 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-11-08 17:50:34 +00:00
stephan
1f6cdf0574 rpirena: trigger LEDs 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2283 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-11-06 20:01:22 +00:00
stephan
8d6eef948b direna: synth syntaxc fix 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2275 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-11-03 11:32:46 +00:00
stephan
0d53bd3c40 rpirena: implement and use irena_core, direna filter with flyrena trigger 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2261 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-10-28 00:30:57 +00:00
stephan
551e56ceeb direna ADC channel: 
add outputs for flyrena trigger
   update port syntax
   add parameter for number of channels
   use generate


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2260 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-10-28 00:30:03 +00:00
stephan
8f9157daa6 direna_test: 
change timescale
   `ifdef main module to use mega models.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2259 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-10-28 00:28:09 +00:00
stephan
908cc051f4 direna filter: 
rename module to dfilter
   expand float output to 18 bits.
   update port syntax


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2258 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-10-28 00:26:11 +00:00
stephan
57ecaaab3c flyrena sfilter: 
add NT parameter for number of L2 triggers
   allow alternative implementations of ABTto32
   fix bug in samples timestamp emission


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2257 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-10-28 00:23:34 +00:00
stephan
f7cd854e94 pulser sim: fix start value 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2256 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-10-28 00:20:46 +00:00
stephan
c8f4097db0 fix index typo 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2093 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-09-02 16:51:43 +00:00
stephan
4ac3aa3173 packed sample packets 
opheater parameter readout
SPIPE serial master states tranfer cadence parameter


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2085 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-09-01 21:37:58 +00:00
stephan
14f8d969d1 single channel counters as ufloat16 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2053 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-08-26 18:47:11 +00:00
stephan
9437f92995 single channel trigger counters 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2051 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-08-25 23:36:23 +00:00
stephan
1f1f799c80 limit peek data to the available channel data 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2008 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-08-18 20:34:36 +00:00
stephan
d1426a18cb readout all channels for random triggers 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1999 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-08-16 11:55:37 +00:00
stephan
4e3bb009e7 test with sparse mask, gold file 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1992 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-08-15 16:43:50 +00:00
stephan
f93b14355c test L2 masked readout with sparse L2 masks 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1991 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-08-15 16:20:31 +00:00
stephan
9896058681 dranbuf uses L2 mask 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1989 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-08-15 14:07:24 +00:00
stephan
4420ff06cb L2 trigger with mask 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1987 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-08-15 11:22:38 +00:00
stephan
acab3e8a08 fix dranbuf timing for L2 with mask 
fix filter_test and flyrena tests for new L2 config
save flyrena.gold as baseline for future changes


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1982 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-08-14 22:49:16 +00:00
stephan
e01685ce29 add mask to hetept L2 trigger 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1981 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-08-14 16:15:51 +00:00
stephan
58af81ccae move module aschedule from irena to library 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1969 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-08-12 19:23:52 +00:00
stephan
b5dc83ce32 move ADC128S102 model into the general library 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1966 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-08-12 15:16:02 +00:00
stephan
3d8c1638d4 flyrena sim with EPT event generator 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1926 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-07-12 13:23:39 +00:00
stephan
c88a3aff08 flyrena syntax and synthesis clean. Next: simulation 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1900 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-07-08 22:12:19 +00:00
stephan
e689182d34 getting flyrena into flight shape ... 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1891 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-07-07 22:39:56 +00:00