NMRENA v2 boards are ready for 10LC25 FPGAs, which have six fewer IO pins.
The GB1 barometer does not fit.
This version includes a driver for the preamp slow control via the nm64_lvds
adapter board. The new onboard LVDS driver must be omited, the input connected
to one output on the fottprint. The outher output must be connected to an
apropriate power for the LDVS drivers on the adapter.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@8375 bc5caf13-1734-44f8-af43-603852e9ee25
The 10LC24E144 provides six more GND pins instead of IO.
The AIO pins are repurposed for IOs that need to be relocated.
AIO[6] is placed on a spare pin 8, that becomes available with
RESERVE_FLASH_NCE_AFTER_CONFIGURATION.
AOI[5] is driving an LVDS driver to CONN20-ATx[5-,6+].
AIO[7:8] are dropped. The GB1 port is disabled.
CONN20-ATx[7,8] are connected to ARM Ains with NTC pullup.
TODO next: TARGET_10LC25
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@8277 bc5caf13-1734-44f8-af43-603852e9ee25
