We were loosing data items in the science packets.
The go_wim and go_enc counters differed, there were go_enc missing.
Hypothesis: win_sum_valid were dropped under memory bus load.
Code review: a memport val shall never be qualified by conditions
unless you can make absolutely sure you get exactly all the val you need.
This patch reimplements memwindow.valid and memwindow.busy
so that we always get a valid after a go, and the busy is long enough
to prevent the dps to gobble up a window to fast.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4421 bc5caf13-1734-44f8-af43-603852e9ee25
use the spare bank 0x30 counter for dps and tfifo events
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4405 bc5caf13-1734-44f8-af43-603852e9ee25
The user of this port have been moved to spare cntrs to bank 0x40.
Debug counters in step_core where removed.
TODO: sirena
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4402 bc5caf13-1734-44f8-af43-603852e9ee25
This command clears all registers to zero.
The register prefetch pipeline will fetch uninitialized
registers which cause repeated EDAC errors.
We may do away with the Z register @R[0]. Z=0xdf instead?
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4355 bc5caf13-1734-44f8-af43-603852e9ee25
Do not wait for the encoder when a zero is added to the input.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4298 bc5caf13-1734-44f8-af43-603852e9ee25
For small count rates it does not make sense to compute
running differences, and that would lead to oszillations.
This patch simplifies the concept how this is handled.
When the number of counts, as reconstructed by the reciever, is less
or equal 8, then the next number will be sent as is, not as a
running difference.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4297 bc5caf13-1734-44f8-af43-603852e9ee25
Make better use of conditional execution.
Use TRIM for histogram bounds
Do not combine Ix1 and Ix2 code.
Implement multiplicity histograms.
Distribute PHA records by energy.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4222 bc5caf13-1734-44f8-af43-603852e9ee25
The secondary L3 trigger instruction pipeline could overflow.
The ififo now pretends to be empty towards the rfifo, if it cannot
push another instruction from the primary to the secondary
instruction fifo.
A POKE target was delivered as eaddr bound for the rfifo to evaluate
if a register read must wait. This could cause the rfifo to read
a register before it was saved. The eaddr is now delivered with an extra
port from the dpath, and always reflects the instruction address, not
the target address.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4221 bc5caf13-1734-44f8-af43-603852e9ee25
The TRIM instruction did not work properly with input data
values between 256 and ul.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4220 bc5caf13-1734-44f8-af43-603852e9ee25
The level 3 trigger was waiting for the completion of slow
instructions even when their condition was not met.
This patch prevents extra wait states when the conditional
if false. The miniumum execution time is 2 mclk. This minimum
is now applied to all instructions which are not executed.
MULI takes 4 mclk when executed
ADD, SUB, LOG take 3 mclk when executed.
Everything else takes 2 mclk.
GOTO takes about 11 mclk when executed, it involves a reset
of the processor, with a pipeline flush.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4219 bc5caf13-1734-44f8-af43-603852e9ee25
por is treated as abort
por resets the opheater
There is a 1 in 256 chance that the por will not happen
if registers initialize randomly at power on.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4152 bc5caf13-1734-44f8-af43-603852e9ee25
Reorganization of reset/abort/atbrk.
Argument size warnings.
Preparation for iverilog 0.10 (git)
Icarus verilog version 0.10 issues warnings for unsized (0)
connected to single ports. These were fixed.
Version 0.10 (git of today) does time 0 initializations
differently. The tfifo used to get reset a time 0, not any
more. A simple reset issued to message() did not succeed,
because undefined state from the tfifo trickles through the tport
chain, to set the message module back to undefined. This was
fixed by wireing abort into tports.
errors[4] = atbrk is fixed. It was always triggering itself
via strobes[0]. Now it really just triggers by the atbrk
sequence.
Gold for step, flyrena, heteptdig.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3978 bc5caf13-1734-44f8-af43-603852e9ee25
When a counter input is stuck high, there will be a deadlock
of the complete memory readback machive as soon as a readback
of that counter memory was started.
Wire up the abort to be able to clear this deadlock.
Todo: consider a timeout.
Todo: consider sending an abort to the counter memory when
any memory readback is started.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3958 bc5caf13-1734-44f8-af43-603852e9ee25
wire TxE to ~confs[5:4], invert EEPROM_nRES
Both LDVS drivers and the EEPROM are enabled when confs==0.
Now we can disable the unused LVDS driver.
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3904 bc5caf13-1734-44f8-af43-603852e9ee25
