Stephan/solo_altera
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Compare commits

base: Stephan:98cd140fa92e74fd429931f634293ebe4def9e87
Branches Tags
Stephan:master
Stephan:thhor
..
compare: Stephan:4d88e31930abc2e948567fdc20464964f5a2e1bb
Branches Tags
Stephan:master
Stephan:thhor

10 commits
98cd140fa9 ... 4d88e31930

Author SHA1 Message Date
stephan
4d88e31930 CSA-Beau-sk: 20×7mm layout 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9402 bc5caf13-1734-44f8-af43-603852e9ee25
 2025-11-17 22:44:33 +00:00
stephan
e2036134d3 tarena: fix hk, drop msg, use pf_match_mask 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9401 bc5caf13-1734-44f8-af43-603852e9ee25
 2025-11-11 21:30:32 +00:00
stephan
8b0d4554d6 ahepam-large-iras: README fix 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9400 bc5caf13-1734-44f8-af43-603852e9ee25
 2025-11-09 20:27:05 +00:00
stephan
a8d1d13cc3 ahepam-large-iras: carrier adaper 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9399 bc5caf13-1734-44f8-af43-603852e9ee25
 2025-11-09 20:24:12 +00:00
stephan
45f97b5aa6 tarena: modern bitfile 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9398 bc5caf13-1734-44f8-af43-603852e9ee25
 2025-11-09 13:20:27 +00:00
stephan
8d2a1ec8b4 lana: status readback 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9397 bc5caf13-1734-44f8-af43-603852e9ee25
 2025-11-09 13:20:03 +00:00
stephan
16e661b92b irena: 9ch/2thr bitfile 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9396 bc5caf13-1734-44f8-af43-603852e9ee25
 2025-11-08 12:44:47 +00:00
stephan
a007e5cfbe nmleia_c3: pinout for nmrena_v1 board 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9395 bc5caf13-1734-44f8-af43-603852e9ee25
 2025-11-05 19:55:31 +00:00
stephan
7dab6493fe nmleia: nmahepam with a single slice 
- dorn: no GTRIGGER, use gtriggrs as etriggers, striggers 
- io: 12 pins remain unused



git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9394 bc5caf13-1734-44f8-af43-603852e9ee25
 2025-11-05 14:43:22 +00:00
stephan
43eaf19be4 ahepam-adc-leia: change Vbias HK range > 100V 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9393 bc5caf13-1734-44f8-af43-603852e9ee25
 2025-10-31 10:16:15 +00:00
21 changed files with 1546 additions and 497 deletions
Download patch file Download diff file Expand all files Collapse all files

19
altera/logicanalyser.v
View file

@ -22,12 +22,12 @@ module logicanalyser
parameter N = 14;
wire [0:5] ree;
wire [15:0] rdd[0:5];
wire [0:6] ree;
wire [15:0] rdd[0:6];
always @(posedge clk)
re <= |ree;
always @(posedge clk)
rd <= rdd[0]|rdd[1]|rdd[2]|rdd[3]|rdd[4]|rdd[5];
rd <= rdd[0]|rdd[1]|rdd[2]|rdd[3]|rdd[4]|rdd[5]|rdd[6];
reg [7:0] ww;
always @(posedge clk)
if (we)
@ -39,14 +39,14 @@ module logicanalyser
wire [15:0] size, pos, conf;
conf_reg siz_r(clk, ww[0], wp, wd, ree[0], rdd[0], size);
conf_reg pos_r(clk, ww[1], wp, wd, ree[1], rdd[1], pos);
conf_reg cnf_r(clk, ww[3], wp, wd, ree[2], rdd[2], conf);
conf_reg #(.NB(N)) h_r(clk, ww[4], wp, wd, ree[3], rdd[3], high);
conf_reg #(.NB(N)) l_r(clk, ww[5], wp, wd, ree[4], rdd[4], low);
conf_reg #(.NB(N)) t_r(clk, ww[6], wp, wd, ree[5], rdd[5], trans);
conf_reg cnf_r(clk, ww[3], wp, wd, ree[3], rdd[3], conf);
conf_reg #(.NB(N)) h_r(clk, ww[4], wp, wd, ree[4], rdd[4], high);
conf_reg #(.NB(N)) l_r(clk, ww[5], wp, wd, ree[5], rdd[5], low);
conf_reg #(.NB(N)) t_r(clk, ww[6], wp, wd, ree[6], rdd[6], trans);
wire exten = conf[4];
wire single = conf[5];
reg [15:12] resets;
always @(posedge clk)
if (ww[3] & wp)
@ -93,6 +93,9 @@ module logicanalyser
wire [14:N] filler = 0;
assign ree[2] = ww[2];
assign rdd[2] = ree[2] ? {run, filler, was} : 0;
spififo buffer
(
.clock(clk),

2
altera/mega/pll192l.v
View file

@ -113,7 +113,9 @@ module pll192 (
altpll_component.charge_pump_current_bits = 1,
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 83333,
`ifdef CYCLONE10
altpll_component.intended_device_family = "Cyclone 10 LP",
`endif
altpll_component.loop_filter_c_bits = 0,
altpll_component.loop_filter_r_bits = 24,
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll192",

6
arena/altera/Makefile
View file

@ -6,10 +6,10 @@ VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
%.vvp:
$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v,$^)
vcd/%.lxt: %.vvp
$< -lxt2 | tee $*.log
vcd/%.fst: %.vvp
$< -fst | tee $*.log
.PRECIOUS: vcd/%.lxt
.PRECIOUS: vcd/%.fst
VPATH=.:./virena:./idef-x:./sixs:./adc128:../../altera:../../altera/mega\
:../../stein/altera:../../dorn/altera:../../nm64/altera/\

13
arena/altera/arena.v
View file

@ -334,22 +334,17 @@ module arena
wire [W-1:0] fsiz1;
wire [W-1:0] fhma1 = 0;
wire [W-1:0] fhva1 = 0;
// Unused
// LANA
wire [W-1:0] fsiz2;
wire [W-1:0] fhma2 = 0;
wire [W-1:0] fhva2 = 0;
// 2nd FPGA fifo
// IX
wire [W-1:0] fsiz3 = 37-1;
wire [W-1:0] fhma3 = 'h ffff;
wire [W-1:0] fhva3 = 'h 7def;
wire [31:0] m_mask = 'h ffff_ffff;
wire [9:0] m_idx = 35;
wire [9:0] m_offs = 2;
wire [1:0] m_scale = 0;
wire [3:0] m_shift = 0;
wire m_size = 0;
wire [63:0] fsma3 = {5'b0, m_size, m_shift, m_scale, m_offs, m_idx, m_mask};
wire [63:0] fsma3;
pf_match_mask mm3(.m(fsma3), .size(fsiz3[9:0]), .idx(10'd 2), .bits(6'd 32), .words(4'd 1));
`endif
`ifdef DARENA

32
arena/altera/idef-x/tarena.v
View file

@ -129,36 +129,11 @@ module tarena
.we(we & wa[10:1]==TEST_ADDR[10:1]), .wa(wa[0]), .wp(wp), .wd(wd), .re(ree[3]), .rd(rdd[3]),
.TEST(TEST) );
// Messages via SPI
parameter MSG_ADDR = 14'h 0048;
reg msg_en;
wire [13:0] msg_ad = wd[13:0];
wire [1:0] msg_sz = wd[15:14];
reg [63:0] msg_da;
always @(posedge clk)
if (we & wp & wa[10:3]==MSG_ADDR[10:3])
if (wa[2])
msg_en <= 1;
else
begin
msg_en <= 0;
case (wa[1:0])
0: msg_da[15:0] <= wd;
1: msg_da[31:16] <= wd;
2: msg_da[47:32] <= wd;
3: msg_da[63:48] <= wd;
endcase
end
else
msg_en <= 0;
step_ix #(.FO(FO)) ix
(.clk(clk), .reset(reset), .enable(enable), .trigger(extrig),
.clock(clock),
.we(we & wa[10:3]==IX_ADDR[10:3]), .wa(wa[2:0]), .wp(wp), .wd(wd),
.re(ree[4]), .rd(rdd[4]),
.msg_en(msg_en), .msg_ad(msg_ad), .msg_sz(msg_sz), .msg_da(msg_da), // unused
.TRIG(trig), .STROBE(strobe), .RD(read), .SC(sc), .DIN(din), .DOUT(dout),
.ASCLK(ASCLK), .ASCLKn(ASCLKn), .ACS(ACS), .ACSn(ACSn),
.ASDATAIN(ASDATAIN), .ASDATAOUT(ASDATAOUT),
@ -182,11 +157,6 @@ module step_ix
output reg re,
output reg [15:0] rd,
input msg_en,
input [13:0] msg_ad,
input [1:0] msg_sz,
input [63:0] msg_da,
input TRIG,
output STROBE,
output RD,
@ -461,7 +431,7 @@ module adc_housekeeping
always @(posedge clk)
begin
adc_req <= 'h ff << c;
adc_req <= ('h ff << c) | {7'b0, good};
if (reset)
c <= 8;

8
arena/altera/idef-x/tarena_test.v
View file

@ -177,7 +177,7 @@ module tarena_test;
initial
begin
$dumpfile("vcd/tarena.lxt");
$dumpfile("vcd/tarena.fst");
$dumpvars(0);
#100 spi.verbose = 2;
#100 spi.frame(0);
@ -197,9 +197,9 @@ module tarena_test;
spi.cmdp(dut.TARENA_ADDR+8, 400);
spi.cmdp(dut.TARENA_ADDR+9, 100);
spi.cmdp(dut.TARENA_ADDR+11, 16'b 1111_xxxxxx_10_xxxx);
spi.cmdp(dut.TARENA_ADDR+12, 16'b xxxxxx_0000000010);
spi.cmdp(dut.TARENA_ADDR+13, 16'b xxxxxx_0000000100);
spi.cmdp(dut.TARENA_ADDR+14, 16'b xxxxxx_0000000010);
spi.cmdp(dut.TARENA_ADDR+12, 16'b xx_00000000000010);
spi.cmdp(dut.TARENA_ADDR+13, 16'b xx_00000000000100);
spi.cmdp(dut.TARENA_ADDR+14, 16'b xx_00000000000010);
#100;
spi.cmdp(IXADDR+1, {4'd15, 1'b0, 3'd 1, 8'd 50});
spi.cmdp(IXADDR+7, {6'd 32, 2'd 3, 4'd 15, 4'd 15});

398
arena/altera/tarena.gold
View file

@ -1,4 +1,27 @@
LXT2 info: dumpfile vcd/tarena.lxt opened for output.
Compiling VVP ...
... VVP file version 12.0 (devel) (s20150603-553-g6c39348d)
Compile cleanup...
... 1536 functors (net_fun pool=524288 bytes)
322 logic
0 bufif
5 resolv
678 signals
... 1426 filters (net_fil pool=524288 bytes)
... 8948 opcodes (221184 bytes)
... 1836 nets
... 1536 vvp_nets (1048544 bytes)
... 7 arrays (37 words)
... 10 memories
10 logic (14888 words)
0 real (0 words)
... 154 scopes
... 0.019291 seconds, 18728.0/10448.0/5272.0 KBytes size/rss/shared
Running ...
...execute EndOfCompile callbacks
...propagate initialization events
...execute StartOfSim callbacks
...run scheduler
FST info: dumpfile vcd/tarena.fst opened for output.
spi frame: sent 0000, received xxxX
spi frame: sent 0000, received 0000
spi frame: sent c00b, received 0000
@ -23,26 +46,126 @@ spi frame: sent 0064, received xxxx
spi frame: sent c80b, received 0000
spi frame: sent fxXx, received xxxx
spi frame: sent c80c, received 0000
spi frame: sent xX02, received xxxx
spi frame: sent X002, received xxxx
spi frame: sent c80d, received 0000
spi frame: sent xX04, received xxxx
spi frame: sent X004, received Xxxx
spi frame: sent c80e, received 0000
spi frame: sent xX02, received xxxx
spi frame: sent X002, received Xxxx
spi frame: sent c919, received 0000
spi frame: sent f132, received xxxx
spi frame: sent f132, received Xxxx
spi frame: sent c91f, received 0000
spi frame: sent 83ff, received xxxx
spi frame: sent c918, received 0000
spi frame: sent 2305, received xxxx
spi frame: sent c00a, received 0000
spi frame: sent 0089, received 0000
SCOPE: 0 1 0 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
ix send config addr 1, data( 2) 000000000000000000000000000000000000000000000000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
spi frame: sent c91b, received 0000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
spi frame: sent 0000, received 0000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
spi frame: sent c91a, received 0000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
spi frame: sent 0102, received xxxx
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
ix send config addr 2, data( 3) 000000000000000000000000000000000000000000000004
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
spi frame: sent c91b, received 0000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
spi frame: sent 8000, received xxxx
spi frame: sent c91a, received 0000
spi frame: sent 0203, received xxxx
@ -100,10 +223,10 @@ spi frame: sent 891d, received 0000
88065 CMD temp read (0)
AOUT->Temp1, cnt= 8
AOUT->Temp2, cnt= 9
94114 CMD temp read (0) done!
95760 CMD temp read (0) done!
spi frame: sent 8001, received 0000
spi frame: sent 0000, received 3dd4
IX temp: 15828
spi frame: sent 0000, received 3dd8
IX temp: 15832
spi frame: sent c807, received 0000
spi frame: sent 8xX8, received 0000
spi frame: sent c80b, received 0000
@ -201,90 +324,205 @@ Housekeeping: 'h e206
spi frame: sent 0000, received 0000
spi frame: sent 0000, received 0000
spi frame: sent 8001, received 0000
spi frame: sent 0000, received 0000
Housekeeping: 'h 0000
spi frame: sent 0000, received 7107
Housekeeping: 'h 7107
spi frame: sent 0000, received 0000
spi frame: sent 0000, received 0000
spi frame: sent 8001, received 0000
spi frame: sent 0000, received 0000
Housekeeping: 'h 0000
spi frame: sent 0000, received f207
Housekeeping: 'h f207
SCOPE: 0 1 0 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
=========== Starting new Event, all = 0
DATA - channel: 04 | adc_data1: 02110 | adc_data2: 01986 | diff: 03972
DATA - channel: 07 | adc_data1: 02085 | adc_data2: 02011 | diff: 04022
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
BASELINE: adc_diff: 07916
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
SCOPE: 0 0 1 0x2000
DATA - channel: 04 | adc_diff: 08068
DATA - channel: 07 | adc_diff: 08118
=========== Finishing Event
spi frame: sent 8000, received f132
=========== Starting new Event, all = 1
DATA - channel: 00 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
DATA - channel: 01 | adc_data1: 02048 | adc_data2: 02048 | diff: 00000
DATA - channel: 02 | adc_data1: 02048 | adc_data2: 02048 | diff: 00000
DATA - channel: 03 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
DATA - channel: 04 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
DATA - channel: 05 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
DATA - channel: 06 | adc_data1: 02098 | adc_data2: 01998 | diff: 03996
DATA - channel: 07 | adc_data1: 02098 | adc_data2: 01998 | diff: 03996
DATA - channel: 08 | adc_data1: 02098 | adc_data2: 01998 | diff: 03996
DATA - channel: 09 | adc_data1: 02098 | adc_data2: 01998 | diff: 03996
DATA - channel: 10 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
DATA - channel: 11 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
DATA - channel: 12 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
DATA - channel: 13 | adc_data1: 02048 | adc_data2: 02048 | diff: 00000
DATA - channel: 14 | adc_data1: 02048 | adc_data2: 02048 | diff: 00000
DATA - channel: 15 | adc_data1: 02048 | adc_data2: 02048 | diff: 00000
DATA - channel: 16 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
DATA - channel: 17 | adc_data1: 02048 | adc_data2: 02048 | diff: 00000
DATA - channel: 18 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
DATA - channel: 19 | adc_data1: 02048 | adc_data2: 02048 | diff: 00000
DATA - channel: 20 | adc_data1: 02048 | adc_data2: 02048 | diff: 00000
DATA - channel: 21 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
DATA - channel: 22 | adc_data1: 02048 | adc_data2: 02048 | diff: 00000
DATA - channel: 23 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
DATA - channel: 24 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
BASELINE: adc_diff: 08118
DATA - channel: 00 | adc_diff: 08190
DATA - channel: 01 | adc_diff: 00000
DATA - channel: 02 | adc_diff: 00000
DATA - channel: 03 | adc_diff: 08190
DATA - channel: 04 | adc_diff: 08190
DATA - channel: 05 | adc_diff: 08190
DATA - channel: 06 | adc_diff: 08092
DATA - channel: 07 | adc_diff: 08092
DATA - channel: 08 | adc_diff: 08092
DATA - channel: 09 | adc_diff: 08092
DATA - channel: 10 | adc_diff: 08190
DATA - channel: 11 | adc_diff: 08190
DATA - channel: 12 | adc_diff: 08190
DATA - channel: 13 | adc_diff: 00000
DATA - channel: 14 | adc_diff: 00000
DATA - channel: 15 | adc_diff: 00000
DATA - channel: 16 | adc_diff: 08190
DATA - channel: 17 | adc_diff: 00000
DATA - channel: 18 | adc_diff: 08190
DATA - channel: 19 | adc_diff: 00000
DATA - channel: 20 | adc_diff: 00000
DATA - channel: 21 | adc_diff: 08190
DATA - channel: 22 | adc_diff: 00000
DATA - channel: 23 | adc_diff: 08190
DATA - channel: 24 | adc_diff: 08190
spi frame: sent 8000, received 7def
DATA - channel: 25 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
DATA - channel: 25 | adc_diff: 08190
spi frame: sent 8000, received 0090
spi frame: sent 8000, received 008b
DATA - channel: 26 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
spi frame: sent 8000, received c098
spi frame: sent 8000, received c0ca
DATA - channel: 27 | adc_data1: 02048 | adc_data2: 02048 | diff: 00000
DATA - channel: 28 | adc_data1: 02048 | adc_data2: 02048 | diff: 00000
DATA - channel: 29 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
DATA - channel: 30 | adc_data1: 02049 | adc_data2: 02047 | diff: 04094
DATA - channel: 31 | adc_data1: 02048 | adc_data2: 02048 | diff: 00000
DATA - channel: 26 | adc_diff: 08190
spi frame: sent 8000, received 0098
spi frame: sent 8000, received 00ca
DATA - channel: 27 | adc_diff: 00000
DATA - channel: 28 | adc_diff: 00000
DATA - channel: 29 | adc_diff: 08190
DATA - channel: 30 | adc_diff: 08190
DATA - channel: 31 | adc_diff: 00000
=========== Finishing Event
spi frame: sent 8000, received 7def
spi frame: sent 8000, received ffff
spi frame: sent 8000, received ffff
spi frame: sent 8000, received 00d6
spi frame: sent 8000, received c048
spi frame: sent 8000, received c04a
spi frame: sent 8000, received c04a
spi frame: sent 8000, received c048
spi frame: sent 8000, received c048
spi frame: sent 8000, received c048
spi frame: sent 8000, received ffe6
spi frame: sent 8000, received ffe6
spi frame: sent 8000, received ffe6
spi frame: sent 8000, received ffe6
spi frame: sent 8000, received c048
spi frame: sent 8000, received c048
spi frame: sent 8000, received c048
spi frame: sent 8000, received c04a
spi frame: sent 8000, received c04a
spi frame: sent 8000, received c04a
spi frame: sent 8000, received c048
spi frame: sent 8000, received c04a
spi frame: sent 8000, received c048
spi frame: sent 8000, received c04a
spi frame: sent 8000, received c04a
spi frame: sent 8000, received c048
spi frame: sent 8000, received c04a
spi frame: sent 8000, received c048
spi frame: sent 8000, received c048
spi frame: sent 8000, received c048
spi frame: sent 8000, received c048
spi frame: sent 8000, received c04a
spi frame: sent 8000, received c04a
spi frame: sent 8000, received c048
spi frame: sent 8000, received c048
spi frame: sent 8000, received c04a
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 004a
spi frame: sent 8000, received 004a
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 3fe6
spi frame: sent 8000, received 3fe6
spi frame: sent 8000, received 3fe6
spi frame: sent 8000, received 3fe6
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 004a
spi frame: sent 8000, received 004a
spi frame: sent 8000, received 004a
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 004a
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 004a
spi frame: sent 8000, received 004a
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 004a
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 004a
spi frame: sent 8000, received 004a
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 0048
spi frame: sent 8000, received 004a
./idef-x/tarena_test.v:245: $finish called at 356105000 (1ps)
...execute Postsim callbacks
... 4.71498 seconds, 19468.0/11204.0/5444.0 KBytes size/rss/shared
Event counts:
200410 time steps (pool=113)
337074 thread schedule events
11878072 assign events
...assign(vec4) pool=9362
...assign(vec8) pool=204
...assign(real) pool=256
...assign(word) pool=128
...assign(word/r) pool=204
313061 other events (pool=4096)

313
arena/altera/tarena.gtkw
View file

@ -1,35 +1,32 @@
[*]
[*] GTKWave Analyzer v3.3.62 (w)1999-2014 BSI
[*] Sun Oct 26 02:00:26 2014
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Sat Nov 8 16:05:29 2025
[*]
[dumpfile] "/data/blaulicht/stephan/tmp/vcd/arena/tarena.lxt"
[dumpfile_mtime] "Sun Oct 26 01:56:06 2014"
[dumpfile_size] 2034330
[dumpfile] "/data/blaulicht/stephan/tmp/vcd/arena/tarena.fst"
[dumpfile_mtime] "Sat Nov 8 15:55:08 2025"
[dumpfile_size] 710873
[savefile] "/home/blaulicht/stephan/svn@asterix/solo/eda/arena/altera/tarena.gtkw"
[timestart] 0
[size] 1848 1172
[pos] -1 -1
*-25.724031 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[size] 1832 1130
[pos] 15 -1
*-25.765026 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tarena_test.
[treeopen] tarena_test.dut.
[treeopen] tarena_test.dut.core.
[treeopen] tarena_test.dut.core.ix.
[treeopen] tarena_test.dut.core.ix.stein_ix_controller.
[treeopen] tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.
[treeopen] tarena_test.dut.front.
[treeopen] tarena_test.dut.front.f1.
[treeopen] tarena_test.dut.front.f3.
[sst_width] 210
[sst_width] 269
[signals_width] 294
[sst_expanded] 1
[sst_vpaned_height] 355
@28
tarena_test.dut.mclk[0]
[sst_vpaned_height] 357
@c00200
-ADC
@22
tarena_test.dut.core.ix.adc_request[7:0]
@28
tarena_test.dut.core.ix.ix_adc_req[0]
tarena_test.dut.core.ix.ix_adc_req_temp[0]
(0)tarena_test.dut.core.ix.stein_adc_controller.ADC_CS[1:2]
(0)tarena_test.dut.core.ix.stein_adc_controller.ADC_SCLK[1:2]
(0)tarena_test.dut.core.ix.stein_adc_controller.ADC_DOUT[1:2]
@ -43,20 +40,8 @@ tarena_test.dut.core.ix.stein_adc_controller.adc_chn[2:0]
@22
tarena_test.dut.core.ix.stein_adc_controller.adc_d1[11:0]
tarena_test.dut.core.ix.stein_adc_controller.adc_d2[11:0]
@28
tarena_test.dut.core.ix.stein_adc_controller.adc_sampled[0]
tarena_test.dut.core.ix.stein_adc_controller.adc_valid[0]
@c00200
-ADC_SCH
@28
tarena_test.dut.core.ix.stein_adc_controller.scheduler.reset[0]
tarena_test.dut.core.ix.stein_adc_controller.scheduler.resync[0]
tarena_test.dut.core.ix.stein_adc_controller.scheduler.dine[0]
tarena_test.dut.core.ix.stein_adc_controller.scheduler.din1[0]
tarena_test.dut.core.ix.stein_adc_controller.scheduler.dout1[0]
tarena_test.dut.core.ix.stein_adc_controller.scheduler.doute[0]
tarena_test.dut.core.ix.stein_adc_controller.scheduler.mtick[0]
tarena_test.dut.core.ix.stein_adc_controller.scheduler.tick[0]
@800028
tarena_test.dut.core.ix.stein_adc_controller.dv[1:3]
@28
@ -74,21 +59,10 @@ tarena_test.dut.core.ix.stein_adc_controller.adc_add[2:0]
-ADC
@c00200
-SPI
@28
tarena_test.dut.spi_sck[0]
tarena_test.dut.spi_mosi[0]
tarena_test.dut.spi_miso[0]
tarena_test.dut.we[0]
tarena_test.dut.wp[0]
@22
tarena_test.dut.wa[13:0]
tarena_test.dut.wd[15:0]
@28
tarena_test.dut.re[0]
@22
tarena_test.dut.rd[15:0]
@28
tarena_test.dut.core.ix.reset[0]
@c00022
tarena_test.dut.core.ix.ww[7:0]
@28
@ -140,9 +114,6 @@ tarena_test.dut.core.ix.temp[13:0]
-RD
@c00200
-HK
@28
tarena_test.dut.core.ix.hk.go[0]
tarena_test.dut.core.ix.hk.reset[0]
@24
tarena_test.dut.core.ix.hk.adc_channel[2:0]
@28
@ -151,66 +122,24 @@ tarena_test.dut.core.ix.adc_chn[2:0]
tarena_test.dut.core.ix.hk.adc_d1[11:0]
tarena_test.dut.core.ix.hk.adc_d2[11:0]
tarena_test.dut.core.ix.hk.adc_req[7:0]
@28
tarena_test.dut.core.ix.hk.adc_s[0]
tarena_test.dut.core.ix.hk.adc_v[0]
tarena_test.dut.core.ix.hk.adc_val[0]
@22
tarena_test.dut.core.ix.hk.c[3:0]
@28
tarena_test.dut.core.ix.hk.re[0]
@22
tarena_test.dut.core.ix.hk.rd[15:0]
@1401200
-HK
@c00200
-TEMP
@28
tarena_test.dut.core.ix.ix_temp.reset[0]
tarena_test.dut.core.ix.ix_temp.go[0]
tarena_test.dut.core.ix.ix_temp.busy[0]
tarena_test.dut.core.ix.ix_temp.SC[0]
tarena_test.dut.core.ix.ix_temp.STROBE[0]
tarena_test.dut.core.ix.ix_temp.DIN[0]
tarena_test.dut.core.ix.ix_temp.adc_channel[2:0]
tarena_test.dut.core.ix.ix_temp.as[0]
tarena_test.dut.core.ix.ix_temp.av[0]
@22
tarena_test.dut.core.ix.ix_temp.cdiv[9:0]
@28
tarena_test.dut.core.ix.ix_temp.tick[0]
@22
tarena_test.dut.core.ix.ix_temp.n[3:0]
@28
tarena_test.dut.core.ix.ix_temp.sampled[0]
tarena_test.dut.core.ix.ix_temp.stopreq[0]
@420
tarena_test.dut.core.ix.ix_temp.temp[13:0]
@1401200
-TEMP
@800200
@c00200
-ACQUIRE
@28
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.TRIG[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.RD[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.STROBE[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.DIN[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.DOUT[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.start[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.tick[0]
@24
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.n[5:0]
@28
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.eon[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.eom[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.nn[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.mm[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.mm1[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.nn1[0]
@24
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.m[5:0]
@28
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.nnn[0]
@c00028
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.dout_pipe[1:0]
@28
@ -218,130 +147,53 @@ tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.dout_pipe[1:0]
(1)tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.dout_pipe[1:0]
@1401200
-group_end
@28
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.dtick[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.tdelay[0]
@22
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.tokens[31:0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.token[31:0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.chn_nr[4:0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.channel_nr[4:0]
@28
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.dout[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.mutick[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.adc_req[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.adc_s[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.adc_v[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.acq_settled[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.wait_adcv[0]
tarena_test.dut.core.ix.enable[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.adc_req[0]
tarena_test.dut.core.ix.ack[0]
tarena_test.dut.core.ix.nack[0]
@22
tarena_test.dut.core.ix.baseline[12:0]
@24
tarena_test.dut.core.ix.clock[31:0]
@22
tarena_test.dut.core.ix.data[63:0]
@28
tarena_test.dut.core.ix.e_done[0]
tarena_test.dut.core.ix.e_next[0]
tarena_test.dut.core.ix.e_start[0]
tarena_test.dut.core.ix.fifoe[0]
@23
tarena_test.dut.core.ix.fifo[15:0]
@800200
-L2TRIG
@28
tarena_test.dut.core.ix.stein_ix_controller.tokene[0]
@22
tarena_test.dut.core.ix.token[31:0]
tarena_test.dut.core.ix.stein_ix_controller.dtime[7:0]
@28
tarena_test.dut.core.ix.stein_ix_controller.l2trig.ack[0]
tarena_test.dut.core.ix.stein_ix_controller.l2trig.nack[0]
tarena_test.dut.core.ix.stein_ix_controller.l2cls[1:0]
tarena_test.dut.core.ix.stein_ix_controller.l2trig.too_fast[0]
tarena_test.dut.core.ix.stein_ix_controller.l2trig.too_few[0]
tarena_test.dut.core.ix.stein_ix_controller.l2trig.too_many[0]
tarena_test.dut.core.ix.stein_ix_controller.l2trig.too_many_bg[0]
tarena_test.dut.core.ix.stein_ix_controller.l2trig.too_many_large[0]
tarena_test.dut.core.ix.stein_ix_controller.l2trig.too_many_small[0]
tarena_test.dut.core.ix.stein_ix_controller.l2trig.bp[1:0]
@22
tarena_test.dut.core.ix.stein_ix_controller.l2trig.lp[3:0]
tarena_test.dut.core.ix.stein_ix_controller.l2trig.sp[3:0]
tarena_test.dut.core.ix.stein_ix_controller.l2trig.sum[4:0]
@1000200
-L2TRIG
@28
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.timeout[0]
@22
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.timeout_counter[5:0]
@28
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.timeout_len[2:0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.timeouts[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.reset[0]
@22
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.stream[15:0]
@28
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.stream_ack[0]
tarena_test.dut.core.ix.stein_ix_controller.ix_acquire.stream_en[0]
tarena_test.dut.core.ix.hss[0]
@1000200
@1401200
-ACQUIRE
@c00200
-FIFO
@28
tarena_test.dut.front.f3.reset[0]
tarena_test.dut.front.f3.push[0]
@22
tarena_test.dut.front.f3.data[15:0]
@28
tarena_test.dut.front.f3.empty[0]
tarena_test.dut.front.f3.full[0]
tarena_test.dut.front.f3.ffull[0]
@22
tarena_test.dut.front.f3.used[10:0]
tarena_test.dut.front.f3.have[12:0]
tarena_test.dut.front.f3.free[12:0]
@28
tarena_test.dut.front.f3.packet[0]
tarena_test.dut.front.f3.halffull[0]
tarena_test.dut.front.f3.afull[0]
tarena_test.dut.front.f3.rri[0]
tarena_test.dut.front.f3.rro[0]
tarena_test.dut.front.f3.start[0]
tarena_test.dut.front.f3.search[0]
tarena_test.dut.front.f3.error[0]
tarena_test.dut.front.f3.abort[0]
tarena_test.dut.front.f3.busy[0]
@24
tarena_test.dut.front.f3.count[9:0]
@22
tarena_test.dut.front.f3.fout[15:0]
@28
tarena_test.dut.front.f3.size_match[0]
@22
tarena_test.dut.front.f3.m_count.i[31:0]
tarena_test.dut.front.f3.m_count.q[9:0]
tarena_test.dut.front.f3.matched_size[9:0]
@28
tarena_test.dut.front.f3.re[0]
@22
tarena_test.dut.front.f3.rd[15:0]
@1401200
-FIFO
@c00200
-Idef-X
@28
tarena_test.ix.TRIG[0]
tarena_test.ix.RD[0]
tarena_test.ix.SC[0]
tarena_test.ix.STROBE[0]
tarena_test.ix.DIN[0]
tarena_test.ix.DOUT[0]
@18420
tarena_test.ix.AOUT[13:0]
@20000
@ -356,26 +208,15 @@ tarena_test.ix.RSM[3:0]
tarena_test.ix.SELFILTER[2:0]
@22
tarena_test.ix.TEST_REG[31:0]
tarena_test.ix.cnt[31:0]
@28
tarena_test.ix.r_wb[0]
@22
tarena_test.ix.addr[6:0]
@1401200
-Idef-X
@c00200
-SC
@28
tarena_test.dut.core.ix.s.SC[0]
tarena_test.dut.core.ix.s.STROBE[0]
tarena_test.dut.core.ix.s.DIN[0]
tarena_test.dut.core.ix.s.DOUT[0]
tarena_test.dut.core.ix.s.tick[0]
@22
tarena_test.dut.core.ix.s.bits[7:0]
@28
tarena_test.dut.core.ix.s.cdiv[2:1]
tarena_test.dut.core.ix.s.dout[0]
(199)tarena_test.dut.core.ix.s.sr[199:0]
@c00022
tarena_test.dut.core.ix.s.sr[199:0]
@ -591,21 +432,123 @@ tarena_test.dut.core.ix.s.dout_tick[0:2]
-group_end
@22
tarena_test.dut.core.ix.s.n[7:0]
@28
tarena_test.dut.core.ix.s.nn[0]
@22
tarena_test.dut.core.ix.s.rd[15:0]
@28
tarena_test.dut.core.ix.s.re[0]
tarena_test.dut.core.ix.s.reset[0]
tarena_test.dut.core.ix.s.start[0]
tarena_test.dut.core.ix.s.wa[0]
@22
tarena_test.dut.core.ix.s.wd[15:0]
@28
tarena_test.dut.core.ix.s.we[0]
tarena_test.dut.core.ix.s.wp[0]
@1401200
-SC
@c00200
-IX
@28
tarena_test.dut.TRIG
tarena_test.dut.RD
tarena_test.dut.SC
tarena_test.dut.STROBE
tarena_test.dut.DIN
tarena_test.dut.DOUT
@1401200
-IX
@c00201
-LANA
@29
tarena_test.dut.core.lana.we
@c00023
tarena_test.dut.core.lana.ww[7:0]
@28
(0)tarena_test.dut.core.lana.ww[7:0]
(1)tarena_test.dut.core.lana.ww[7:0]
(2)tarena_test.dut.core.lana.ww[7:0]
(3)tarena_test.dut.core.lana.ww[7:0]
(4)tarena_test.dut.core.lana.ww[7:0]
(5)tarena_test.dut.core.lana.ww[7:0]
(6)tarena_test.dut.core.lana.ww[7:0]
(7)tarena_test.dut.core.lana.ww[7:0]
@1401201
-group_end
@c00023
tarena_test.dut.core.lana.resets[15:12]
@28
(0)tarena_test.dut.core.lana.resets[15:12]
(1)tarena_test.dut.core.lana.resets[15:12]
(2)tarena_test.dut.core.lana.resets[15:12]
(3)tarena_test.dut.core.lana.resets[15:12]
@1401201
-group_end
@29
tarena_test.dut.core.lana.single
tarena_test.dut.core.lana.run
tarena_test.dut.core.lana.trigger
tarena_test.dut.core.lana.active
@23
tarena_test.dut.core.lana.count[9:0]
@29
tarena_test.dut.core.lana.fifo_push
tarena_test.dut.core.lana.dflg[15:14]
@23
tarena_test.dut.core.lana.size[15:0]
tarena_test.dut.core.lana.pos[15:0]
@29
tarena_test.dut.core.lana.exten
@23
tarena_test.dut.core.lana.trans[13:0]
tarena_test.dut.core.lana.used[11:0]
@29
tarena_test.dut.core.lana.filler[14]
@23
tarena_test.dut.core.lana.fifo_size[15:0]
@29
tarena_test.dut.core.lana.fifo_full
tarena_test.dut.core.lana.extrig
@c00023
tarena_test.dut.core.lana.data[13:0]
@28
(0)tarena_test.dut.core.lana.data[13:0]
(1)tarena_test.dut.core.lana.data[13:0]
(2)tarena_test.dut.core.lana.data[13:0]
(3)tarena_test.dut.core.lana.data[13:0]
(4)tarena_test.dut.core.lana.data[13:0]
(5)tarena_test.dut.core.lana.data[13:0]
(6)tarena_test.dut.core.lana.data[13:0]
(7)tarena_test.dut.core.lana.data[13:0]
(8)tarena_test.dut.core.lana.data[13:0]
(9)tarena_test.dut.core.lana.data[13:0]
(10)tarena_test.dut.core.lana.data[13:0]
(11)tarena_test.dut.core.lana.data[13:0]
(12)tarena_test.dut.core.lana.data[13:0]
(13)tarena_test.dut.core.lana.data[13:0]
@1401201
-group_end
@23
tarena_test.dut.core.lana.was[13:0]
tarena_test.dut.core.lana.now[13:0]
tarena_test.dut.core.lana.low[13:0]
tarena_test.dut.core.lana.high[13:0]
tarena_test.dut.core.lana.ledged[13:0]
@c00023
tarena_test.dut.core.lana.edged[13:0]
@28
(0)tarena_test.dut.core.lana.edged[13:0]
(1)tarena_test.dut.core.lana.edged[13:0]
(2)tarena_test.dut.core.lana.edged[13:0]
(3)tarena_test.dut.core.lana.edged[13:0]
(4)tarena_test.dut.core.lana.edged[13:0]
(5)tarena_test.dut.core.lana.edged[13:0]
(6)tarena_test.dut.core.lana.edged[13:0]
(7)tarena_test.dut.core.lana.edged[13:0]
(8)tarena_test.dut.core.lana.edged[13:0]
(9)tarena_test.dut.core.lana.edged[13:0]
(10)tarena_test.dut.core.lana.edged[13:0]
(11)tarena_test.dut.core.lana.edged[13:0]
(12)tarena_test.dut.core.lana.edged[13:0]
(13)tarena_test.dut.core.lana.edged[13:0]
@1401201
-group_end
@29
tarena_test.dut.front.f2.push
tarena_test.dut.front.f2.empty
tarena_test.dut.front.f2.packet
tarena_test.dut.front.f3.start
tarena_test.dut.front.f3.packet
@1401201
-LANA
[pattern_trace] 1
[pattern_trace] 0

2
arena/altera/tarena.qsf
View file

@ -225,6 +225,6 @@ set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_MACRO "TARENA=1"
set_global_assignment -name VERILOG_MACRO "TARGET_ALTERA=1"
set_global_assignment -name VERILOG_MACRO "COUNTBITS_BTREE=1"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

270
arena/altera/tarena.warnings
View file

@ -1,140 +1,178 @@
quartus/tarena.asm.rpt:Info: Quartus II Assembler was successful. 0 errors, 0 warnings
quartus/tarena.asm.rpt:Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
quartus/tarena.fit.rpt: 5. I/O Assignment Warnings
quartus/tarena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
quartus/tarena.fit.rpt:; I/O Assignment Warnings ;
quartus/tarena.fit.rpt:Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
quartus/tarena.fit.rpt:Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
quartus/tarena.fit.rpt:Warning: Following 10 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
quartus/tarena.fit.rpt: Warning: Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
quartus/tarena.fit.rpt: Warning: Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
quartus/tarena.fit.rpt: Warning: Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
quartus/tarena.fit.rpt: Warning: Pin "adc_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "adc_clk(n)"
quartus/tarena.fit.rpt: Warning: Pin "ARx[3]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[3](n)"
quartus/tarena.fit.rpt: Warning: Pin "ARx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[1](n)"
quartus/tarena.fit.rpt: Warning: Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
quartus/tarena.fit.rpt: Warning: Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
quartus/tarena.fit.rpt: Warning: Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
quartus/tarena.fit.rpt: Warning: Pin "ARx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[2](n)"
quartus/tarena.fit.rpt:Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/tarena.fit.rpt:Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/tarena.fit.rpt:Warning: Following 14 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
quartus/tarena.fit.rpt:Info: Quartus II Fitter was successful. 0 errors, 16 warnings
quartus/tarena.map.rpt:; resync ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
quartus/tarena.map.rpt:; n ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; rbi ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
quartus/tarena.map.rpt:; halffull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; c1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; c2 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; c3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; c4 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/tarena.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
quartus/tarena.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
quartus/tarena.fit.rpt:Warning (176674): Following 10 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
quartus/tarena.fit.rpt: Warning (176118): Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
quartus/tarena.fit.rpt: Warning (176118): Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
quartus/tarena.fit.rpt: Warning (176118): Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
quartus/tarena.fit.rpt: Warning (176118): Pin "adc_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "adc_clk(n)"
quartus/tarena.fit.rpt: Warning (176118): Pin "ARx[3]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[3](n)"
quartus/tarena.fit.rpt: Warning (176118): Pin "ARx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[1](n)"
quartus/tarena.fit.rpt: Warning (176118): Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
quartus/tarena.fit.rpt: Warning (176118): Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
quartus/tarena.fit.rpt: Warning (176118): Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
quartus/tarena.fit.rpt: Warning (176118): Pin "ARx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[2](n)"
quartus/tarena.fit.rpt:Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/tarena.fit.rpt:Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/tarena.fit.rpt:Warning (169064): Following 14 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
quartus/tarena.fit.rpt:Info: Quartus II 32-bit Fitter was successful. 0 errors, 17 warnings
quartus/tarena.map.rpt:; temp_adc_values ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; too_fast ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; too_few ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; too_many ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; too_many_small ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; too_many_large ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; too_many_bg ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; lss_init ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; lss_put ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; lss_submit ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; timeouts ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; DEBUG ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; n ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; DIN ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; STROBE ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; go ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; monitor ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; STROBEn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; hss ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../stein/altera/stein_adc_controller.v(9)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../stein/altera/stein_ix_controller.v(473)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../stein/altera/stein_ix_controller.v(475)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../stein/altera/stein_ix_controller.v(477)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../stein/altera/stein_ix_controller.v(492)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../stein/altera/stein_ix_controller.v(549)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/serializer.v(188)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(13)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(15)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(63)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(106)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(120)
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at countbits.v(24): Parameter Declaration in module "countbits" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at tarena.v(75): Parameter Declaration in module "tarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at tarena.v(76): Parameter Declaration in module "tarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at tarena.v(77): Parameter Declaration in module "tarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at tarena.v(78): Parameter Declaration in module "tarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at tarena.v(79): Parameter Declaration in module "tarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at tarena.v(133): Parameter Declaration in module "tarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ix.v(229): Parameter Declaration in module "ix_slow_control" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ix.v(230): Parameter Declaration in module "ix_slow_control" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at barrel.v(9): Parameter Declaration in module "barrel" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at priority_encoder.v(8): Parameter Declaration in module "priority_encode" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stein_ix_controller.v(482): Parameter Declaration in module "stein_ix_slow_control" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stein_ix_controller.v(483): Parameter Declaration in module "stein_ix_slow_control" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stein_ix_controller.v(484): Parameter Declaration in module "stein_ix_slow_control" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at arena.v(156): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at arena.v(269): truncated value with size 32 to match size of target (16)
quartus/tarena.map.rpt:Warning (10034): Output port "debug[4..6]" at arena.v(42) has no driver
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at arena.v(235): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at arena.v(342): truncated value with size 32 to match size of target (16)
quartus/tarena.map.rpt:Warning (10034): Output port "debug[4..6]" at arena.v(80) has no driver
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(253): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(255): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(141): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(159): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(12): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(256): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(258): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(71): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(152): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(173): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10034): Output port "hss" at tarena.v(53) has no driver
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_master_adc.v(99): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc_data.v(25): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at oscilloscope.v(75): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc_data.v(27): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at oscilloscope.v(78): truncated value with size 32 to match size of target (12)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at oscilloscope.v(140): truncated value with size 32 to match size of target (16)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at logicanalyser.v(74): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(59): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(61): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(63): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at logicanalyser.v(97): truncated value with size 32 to match size of target (16)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(60): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(62): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(64): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(80): truncated value with size 32 to match size of target (20)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(100): truncated value with size 32 to match size of target (15)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at tarena.v(316): truncated value with size 5 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at tarena.v(349): truncated value with size 32 to match size of target (16)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(331): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(333): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(349): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(351): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(353): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(249): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(251): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(272): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(274): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_adc_controller.v(56): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(102): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at tarena.v(358): truncated value with size 5 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at tarena.v(391): truncated value with size 32 to match size of target (16)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(343): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(345): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(364): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(366): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(368): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(250): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(252): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(273): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(275): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(283): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_adc_controller.v(75): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(163): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at priority_encoder.v(15): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1021): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1023): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1028): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1030): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1041): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1083): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1105): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1109): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1111): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1208): truncated value with size 32 to match size of target (5)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1210): truncated value with size 32 to match size of target (5)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1227): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1240): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1242): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(497): truncated value with size 32 to match size of target (12)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(12): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(12): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at tarena.v(449): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(271): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(273): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(287): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(303): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(305): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(312): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning: Synthesized away the following node(s):
quartus/tarena.map.rpt: Warning: Synthesized away the following RAM node(s):
quartus/tarena.map.rpt: Warning (14320): Synthesized away node "tarena:core|logicanalyser:lana|spififo:buffer|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[14]"
quartus/tarena.map.rpt: Warning (14320): Synthesized away node "tarena:core|oscilloscope:scope|spififo:buffer|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15]"
quartus/tarena.map.rpt:Warning: 4 hierarchies have connectivity warnings - see the Connectivity Checks report folder
quartus/tarena.map.rpt:Warning: The following nodes have both tri-state and non-tri-state drivers
quartus/tarena.map.rpt: Warning: Inserted always-enabled tri-state buffer between "AC[0]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning: Inserted always-enabled tri-state buffer between "AC[1]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning: Inserted always-enabled tri-state buffer between "AC[2]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning: Inserted always-enabled tri-state buffer between "AC[3]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning: Inserted always-enabled tri-state buffer between "AC[4]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning: Inserted always-enabled tri-state buffer between "AC[6]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning: Inserted always-enabled tri-state buffer between "AC[7]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning: Inserted always-enabled tri-state buffer between "AC[8]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning: Inserted always-enabled tri-state buffer between "AC[11]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning: Inserted always-enabled tri-state buffer between "AC[12]" and its non-tri-state driver.
quartus/tarena.map.rpt:Warning: The following bidir pins have no drivers
quartus/tarena.map.rpt: Warning: Bidir "adc_mode" has no driver
quartus/tarena.map.rpt: Warning: Bidir "AC[5]" has no driver
quartus/tarena.map.rpt: Warning: Bidir "AC[9]" has no driver
quartus/tarena.map.rpt: Warning: Bidir "AC[10]" has no driver
quartus/tarena.map.rpt:Warning: TRI or OPNDRN buffers permanently enabled
quartus/tarena.map.rpt: Warning: Node "AC[0]~synth"
quartus/tarena.map.rpt: Warning: Node "AC[1]~synth"
quartus/tarena.map.rpt: Warning: Node "AC[2]~synth"
quartus/tarena.map.rpt: Warning: Node "AC[3]~synth"
quartus/tarena.map.rpt: Warning: Node "AC[4]~synth"
quartus/tarena.map.rpt: Warning: Node "AC[6]~synth"
quartus/tarena.map.rpt: Warning: Node "AC[7]~synth"
quartus/tarena.map.rpt: Warning: Node "AC[8]~synth"
quartus/tarena.map.rpt: Warning: Node "AC[11]~synth"
quartus/tarena.map.rpt: Warning: Node "AC[12]~synth"
quartus/tarena.map.rpt:Warning: Output pins are stuck at VCC or GND
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(972): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(974): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1012): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1061): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1068): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1076): truncated value with size 32 to match size of target (5)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1081): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1092): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1094): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1107): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1113): truncated value with size 32 to match size of target (11)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1175): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1178): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1180): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1225): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1248): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(521): truncated value with size 32 to match size of target (12)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at tarena.v(464): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at tarena.v(471): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(261): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(263): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(274): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(294): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(296): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(303): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (14284): Synthesized away the following node(s):
quartus/tarena.map.rpt: Warning (14285): Synthesized away the following RAM node(s):
quartus/tarena.map.rpt: Warning (14320): Synthesized away node "tarena:core|logicanalyser:lana|spififo:buffer|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[14]"
quartus/tarena.map.rpt: Warning (14320): Synthesized away node "tarena:core|oscilloscope:scope|spififo:buffer|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15]"
quartus/tarena.map.rpt:Warning (12241): 8 hierarchies have connectivity warnings - see the Connectivity Checks report folder
quartus/tarena.map.rpt:Warning (13034): The following nodes have both tri-state and non-tri-state drivers
quartus/tarena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[0]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[1]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[2]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[3]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[4]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[6]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[7]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[8]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[11]" and its non-tri-state driver.
quartus/tarena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[12]" and its non-tri-state driver.
quartus/tarena.map.rpt:Warning (13039): The following bidir pins have no drivers
quartus/tarena.map.rpt: Warning (13040): Bidir "AC[5]" has no driver
quartus/tarena.map.rpt: Warning (13040): Bidir "AC[9]" has no driver
quartus/tarena.map.rpt: Warning (13040): Bidir "AC[10]" has no driver
quartus/tarena.map.rpt: Warning (13040): Bidir "adc_mode" has no driver
quartus/tarena.map.rpt:Warning (13009): TRI or OPNDRN buffers permanently enabled
quartus/tarena.map.rpt: Warning (13010): Node "AC[0]~synth"
quartus/tarena.map.rpt: Warning (13010): Node "AC[1]~synth"
quartus/tarena.map.rpt: Warning (13010): Node "AC[2]~synth"
quartus/tarena.map.rpt: Warning (13010): Node "AC[3]~synth"
quartus/tarena.map.rpt: Warning (13010): Node "AC[4]~synth"
quartus/tarena.map.rpt: Warning (13010): Node "AC[6]~synth"
quartus/tarena.map.rpt: Warning (13010): Node "AC[7]~synth"
quartus/tarena.map.rpt: Warning (13010): Node "AC[8]~synth"
quartus/tarena.map.rpt: Warning (13010): Node "AC[11]~synth"
quartus/tarena.map.rpt: Warning (13010): Node "AC[12]~synth"
quartus/tarena.map.rpt:Warning (13024): Output pins are stuck at VCC or GND
quartus/tarena.map.rpt: Warning (13410): Pin "debug[6]" is stuck at GND
quartus/tarena.map.rpt: Warning (13410): Pin "debug[5]" is stuck at GND
quartus/tarena.map.rpt: Warning (13410): Pin "debug[4]" is stuck at GND
quartus/tarena.map.rpt: Warning (13410): Pin "debug[3]" is stuck at GND
quartus/tarena.map.rpt: Warning (13410): Pin "debug[1]" is stuck at GND
quartus/tarena.map.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
quartus/tarena.map.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
quartus/tarena.map.rpt:Warning: Design contains 6 input pin(s) that do not drive logic
quartus/tarena.map.rpt:Warning (15899): PLL "pll96:pll0|altpll:altpll_component|altpll_lm43:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
quartus/tarena.map.rpt:Warning (21074): Design contains 6 input pin(s) that do not drive logic
quartus/tarena.map.rpt: Warning (15610): No output dependent on input pin "clk_T1"
quartus/tarena.map.rpt: Warning (15610): No output dependent on input pin "trigger"
quartus/tarena.map.rpt: Warning (15610): No output dependent on input pin "Rx[4]"
quartus/tarena.map.rpt: Warning (15610): No output dependent on input pin "Rx[3]"
quartus/tarena.map.rpt: Warning (15610): No output dependent on input pin "ARx[3]"
quartus/tarena.map.rpt: Warning (15610): No output dependent on input pin "ARx[1]"
quartus/tarena.map.rpt:Info: Quartus II Analysis & Synthesis was successful. 0 errors, 109 warnings
quartus/tarena.sta.rpt:Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings
quartus/tarena.map.rpt:Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 134 warnings
quartus/tarena.sta.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/tarena.sta.rpt:Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning

4
dorn/altera/Makefile
View file

@ -115,3 +115,7 @@ $(QDIR)/stis_ana_demo_c$(CYCLONE).rbf: stis_ana_demo.v stis_ana_core.v \
$(QDIR)/nmahepam.rbf: nmahepam.v pll192_test.v frontend_test.v \
spi_slave.v frontend.v conf_reg.v packetfifo.v countbits.v \
stis_ana_core.v dorn.v
$(QDIR)/nmleia.rbf: nmahepam.v pll192_test.v frontend_test.v \
spi_slave.v frontend.v conf_reg.v packetfifo.v countbits.v \
stis_ana_core.v dorn.v

11
dorn/altera/dorn.v
View file

@ -348,6 +348,13 @@ module dorn_core
wire [NT-1:0] gtriggers = trigger_enables[2*NT-1:NT];
wire gsa_enable = trigger_enables[57];
wire csa_enable = trigger_enables[56];
`ifdef WITH_GTRIGGER
wire [NT-1:0] etriggers = {NT{1'b1}};
wire [NT-1:0] striggers = atriggers;
`else
wire [NT-1:0] etriggers = ~gtriggers;
wire [NT-1:0] striggers = etriggers;
`endif
conf_reg te_reg(dclk, ww[TRIG_EN_ADDR], conf_wp, conf_wd, ree[1], rdd[1], trigger_enables[15:0]);
conf_reg ae_reg(dclk, ww[TRIG_AEN_ADDR], conf_wp, conf_wd, ree[2], rdd[2], trigger_enables[31:16]);
conf_reg se_reg(dclk, ww[SA_TRIG_ADDR], conf_wp, conf_wd, ree[3], rdd[3], trigger_enables[47:32]);
@ -425,10 +432,10 @@ module dorn_core
// - any `atriggers` channel triggered, when `csa_enable`
// - the other slice triggered, when `gsa_enable`
wire [NT-1:0] l2_triggers = ctriggers
wire [NT-1:0] l2_triggers = ctriggers & etriggers
| (trigger ? atriggers : 0)
| (gtrigger ? gtriggers : 0);
wire samples_triggered = |(ctriggers & atriggers) & csa_enable
wire samples_triggered = |(ctriggers & striggers) & csa_enable
| gtrigger & gsa_enable;
`endif

103
dorn/altera/nmahepam.v
View file

@ -1,70 +1,66 @@
`define NMRENA_v2
module nmrena
(
input clk_12,
input clk_T1,
input spi_sck,
input spi_mosi,
output spi_miso,
input clk_12,
input clk_T1,
input spi_sck,
input spi_mosi,
output spi_miso,
output attn,
input trigger,
output attn,
input trigger,
// Barometer
output pt_MCLK,
output pt_SCLK,
output pt_Din,
input pt_Dout,
output pt_MCLK,
output pt_SCLK,
output pt_Din,
input pt_Dout,
// RS232
input [1:4] SRx,
output [1:4] STx,
input [1:4] SRx,
output [1:4] STx,
// I2C
inout [1:4] ATx,
inout [1:4] ATx,
// LVDS
input [1:3] ARx,
`ifndef NMRENA_v2
inout [5:8] AIO,
`else
inout [5:6] AIO,
`endif
input [1:3] ARx,
inout [5:6] AIO,
// ADC
output ADC_nRES,
output ADC_SDI,
input ADC_SDO,
output ADC_SCK,
output ADC_nCE,
output ADC_nRES,
output ADC_SDI,
input ADC_SDO,
output ADC_SCK,
output ADC_nCE,
// DAC
output DAC_SDI,
output DAC_SCK,
output DAC_nCS,
output DAC_SDI,
output DAC_SCK,
output DAC_nCS,
// Thresholds DAC
output THR_SDI,
output THR_SCK,
output THR_nCS,
output THR_SDI,
output THR_SCK,
output THR_nCS,
//inout [23:0] DISC
// DISC new distribution
output [1:0] SCLK, //Serial Clock Output
output [1:0] DIN, //Data Input to DISC Channels
output [1:0] nSCLK,
output [1:0] nCS, // Chip Select Output
input [7:0] DOUT1, //Data Output from DISC Channels
input [7:0] DOUT0
`ifndef NMRENA_v2
// spares
, output [4:5] debug
output [SLICES-1:0] SCLK, //Serial Clock Output
output [SLICES-1:0] DIN, //Data Input to DISC Channels
output [SLICES-1:0] nSCLK,
output [SLICES-1:0] nCS, // Chip Select Output
input [7:0] DOUT0,
`ifndef NMLEIA
input [7:0] DOUT1 //Data Output from DISC Channels
`else
input [11:0] UNUSED
`endif
);
`ifdef NMLEIA
parameter SLICES = 1;
`else
parameter SLICES = 2;
`endif
parameter ND = 8;
wire pll_locked;
@ -182,12 +178,13 @@ module nmrena
resets_d[3:0] }; // clock, resync, unused, read_fifo
wire [14:0] states = {6'b0, confs_d[1], {4{confs_d[0]}}, 4'b0};
wire [49:0] counter_hit, counter_hit_d;
wire [1:0] stick_d;
parameter NHIT = SLICES*(3*ND+1);
wire [NHIT-1:0] counter_hit, counter_hit_d;
wire [SLICES-1:0] stick_d;
wire [15:0] ev_psize;
//Instantiate stis_ana-core with DISC-connections
stis_ana_core #(.MCLK(32), .SLICES(2), .ND(ND)) ana
stis_ana_core #(.MCLK(32), .SLICES(SLICES), .ND(ND)) ana
( .mclk(dclk),
.conf_strobes(strobes), .conf_states(states),
.conf_we(we_d), .conf_wp(wp_d), .conf_wa(wa_d), .conf_wd(wd_d),
@ -196,7 +193,11 @@ module nmrena
.ev_psize(ev_psize),
.counter_hit(counter_hit_d), .stick(stick_d),
.SCLK(SCLK), .nCS(nCS), .DIN(DIN),
`ifndef NMLEIA
.DOUT({DOUT1,DOUT0})
`else
.DOUT(DOUT0)
`endif
);
// ¡ quartus synthesizes an IO REG :) !
@ -211,7 +212,7 @@ module nmrena
.sdata(1'b0),
.fpush(stick) );
sclk_to_fclk #(.D(50), .Z(1)) s2f_chit
sclk_to_fclk #(.D(NHIT), .Z(1)) s2f_chit
( .sclk(dclk), .fclk(mclk),
.spush(|counter_hit_d),
.sdata(counter_hit_d),
@ -286,7 +287,7 @@ module nmrena
parameter CNTR_ADDR = 'h 240;
wire read_counters = we & wa[13:4]==CNTR_ADDR[13:4];
assign fhma[FIFO_CNTR] = 16'h ffff;
nm_counters #(.N(50)) counters
nm_counters #(.N(NHIT)) counters
(
.clk(mclk),
.clear(resets[1] | read_counters & wa[2] & (~fifo_full[FIFO_CNTR] | ~wa[3])),

32
dorn/altera/nmleia.qpf Normal file
View file

@ -0,0 +1,32 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 13:40:26 November 05, 2025
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "20.1"
DATE = "13:40:26 November 05, 2025"
# Revisions
PROJECT_REVISION = "nmleia"
PROJECT_REVISION = "nmahepam"

287
dorn/altera/nmleia.qsf Normal file
View file

@ -0,0 +1,287 @@
# -*- tcl -*-
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# irena_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY quartus
set_global_assignment -name DEVICE 10CL025YE144I7G
set_global_assignment -name TOP_LEVEL_ENTITY nmrena
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name MISC_FILE nmrenav2.dpf
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name CRC_ERROR_CHECKING ON
set_global_assignment -name FORCE_CONFIGURATION_VCCIO OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name EDA_SIMULATION_TOOL "Custom Verilog HDL"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# IRENA
set_instance_assignment -name IO_STANDARD LVDS -to clk_12
set_location_assignment PIN_22 -to clk_12
set_location_assignment PIN_23 -to "clk_12(n)"
set_instance_assignment -name IO_STANDARD LVDS -to clk_T1
set_location_assignment PIN_24 -to clk_T1
set_location_assignment PIN_25 -to "clk_T1(n)"
set_instance_assignment -name IO_STANDARD "2.5 V" -to attn
set_location_assignment PIN_32 -to attn
set_instance_assignment -name IO_STANDARD LVDS -to spi_sck
set_location_assignment PIN_52 -to spi_sck
set_location_assignment PIN_53 -to "spi_sck(n)"
set_instance_assignment -name IO_STANDARD LVDS -to spi_mosi
set_location_assignment PIN_54 -to spi_mosi
set_location_assignment PIN_55 -to "spi_mosi(n)"
set_instance_assignment -name IO_STANDARD LVDS -to spi_miso
set_location_assignment PIN_10 -to spi_miso
set_location_assignment PIN_11 -to "spi_miso(n)"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to spi_miso
set_instance_assignment -name IO_STANDARD LVDS -to trigger
set_location_assignment PIN_129 -to trigger
set_location_assignment PIN_128 -to "trigger(n)"
# Pressure Sensor
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_Dout
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_Din
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_MCLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_SCLK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pt_Din
set_instance_assignment -name FAST_INPUT_REGISTER ON -to pt_Dout
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pt_MCLK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pt_SCLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "8mA" -to pt_Din
set_instance_assignment -name CURRENT_STRENGTH_NEW "8mA" -to pt_MCLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "8mA" -to pt_SCLK
set_instance_assignment -name SLEW_RATE 0 -to pt_Din
set_instance_assignment -name SLEW_RATE 0 -to pt_MCLK
set_instance_assignment -name SLEW_RATE 0 -to pt_SCLK
set_location_assignment PIN_6 -to pt_Dout
set_location_assignment PIN_144 -to pt_Din
set_location_assignment PIN_143 -to pt_MCLK
set_location_assignment PIN_7 -to pt_SCLK
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to pt_Dout
# Serial Ports
set_instance_assignment -name IO_STANDARD "2.5 V" -to SRx
set_instance_assignment -name IO_STANDARD "2.5 V" -to STx
set_location_assignment PIN_136 -to SRx[1]
set_location_assignment PIN_142 -to SRx[2]
set_location_assignment PIN_121 -to SRx[3]
set_location_assignment PIN_135 -to SRx[4]
set_location_assignment PIN_137 -to STx[1]
set_location_assignment PIN_141 -to STx[2]
set_location_assignment PIN_132 -to STx[3]
set_location_assignment PIN_133 -to STx[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SRx
# I2C
set_instance_assignment -name IO_STANDARD LVDS -to ARx
set_instance_assignment -name IO_STANDARD "2.5 V" -to ATx
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ATx
set_instance_assignment -name FAST_INPUT_REGISTER ON -to ATx
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ATx
# LVDS
set_instance_assignment -name IO_STANDARD "2.5 V" -to AIO
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to AIO
set_instance_assignment -name FAST_INPUT_REGISTER ON -to AIO
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to AIO
set_location_assignment PIN_127 -to ARx[1]
set_location_assignment PIN_126 -to "ARx[1](n)"
set_location_assignment PIN_91 -to ARx[2]
set_location_assignment PIN_90 -to "ARx[2](n)"
set_location_assignment PIN_89 -to ARx[3]
set_location_assignment PIN_88 -to "ARx[3](n)"
set_location_assignment PIN_111 -to ATx[1]
set_location_assignment PIN_112 -to ATx[2]
set_location_assignment PIN_113 -to ATx[3]
set_location_assignment PIN_114 -to ATx[4]
set_location_assignment PIN_44 -to AIO[5]
set_location_assignment PIN_8 -to AIO[6]
# ADC
set_instance_assignment -name IO_STANDARD "2.5 V" -to ADC_nRES
set_instance_assignment -name IO_STANDARD "2.5 V" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "2.5 V" -to ADC_SDO
set_instance_assignment -name IO_STANDARD "2.5 V" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "2.5 V" -to ADC_nCE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ADC_SCK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ADC_nCE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ADC_SDI
set_instance_assignment -name FAST_INPUT_REGISTER ON -to ADC_SDO
set_location_assignment PIN_33 -to ADC_nRES
set_location_assignment PIN_31 -to ADC_SDI
set_location_assignment PIN_43 -to ADC_SDO
set_location_assignment PIN_42 -to ADC_SCK
set_location_assignment PIN_39 -to ADC_nCE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ADC_SDO
# DAC
set_instance_assignment -name IO_STANDARD "2.5 V" -to DAC_nCS
set_instance_assignment -name IO_STANDARD "2.5 V" -to DAC_SCK
set_instance_assignment -name IO_STANDARD "2.5 V" -to DAC_SDI
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DAC_SCK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DAC_nCS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DAC_SDI
set_location_assignment PIN_120 -to DAC_nCS
set_location_assignment PIN_119 -to DAC_SCK
set_location_assignment PIN_115 -to DAC_SDI
# Thresholds DAC
set_instance_assignment -name IO_STANDARD "2.5 V" -to THR_nCS
set_instance_assignment -name IO_STANDARD "2.5 V" -to THR_SCK
set_instance_assignment -name IO_STANDARD "2.5 V" -to THR_SDI
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to THR_SCK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to THR_nCS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to THR_SDI
set_location_assignment PIN_103 -to THR_nCS
set_location_assignment PIN_106 -to THR_SCK
set_location_assignment PIN_105 -to THR_SDI
# Discriminator inputs
set_instance_assignment -name IO_STANDARD "2.5 V" -to SCLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to DIN
set_instance_assignment -name IO_STANDARD "2.5 V" -to nSCLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to nCS
set_instance_assignment -name IO_STANDARD "2.5 V" -to DOUT0
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DOUT0
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SCLK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DIN
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nSCLK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DOUT0
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to UNUSED
set_location_assignment PIN_101 -to UNUSED[0]
set_location_assignment PIN_100 -to UNUSED[1]
set_location_assignment PIN_98 -to UNUSED[2]
set_location_assignment PIN_87 -to UNUSED[3]
set_location_assignment PIN_86 -to UNUSED[4]
set_location_assignment PIN_85 -to UNUSED[5]
set_location_assignment PIN_83 -to UNUSED[6]
set_location_assignment PIN_80 -to UNUSED[7]
set_location_assignment PIN_77 -to UNUSED[8]
set_location_assignment PIN_76 -to UNUSED[9]
set_location_assignment PIN_72 -to UNUSED[10]
set_location_assignment PIN_71 -to UNUSED[11]
set_location_assignment PIN_69 -to nCS[0]
set_location_assignment PIN_68 -to DIN[0]
set_location_assignment PIN_67 -to SCLK[0]
set_location_assignment PIN_66 -to nSCLK[0]
set_location_assignment PIN_65 -to DOUT0[7]
set_location_assignment PIN_60 -to DOUT0[6]
set_location_assignment PIN_59 -to DOUT0[5]
set_location_assignment PIN_58 -to DOUT0[4]
set_location_assignment PIN_51 -to DOUT0[3]
set_location_assignment PIN_50 -to DOUT0[2]
set_location_assignment PIN_49 -to DOUT0[1]
set_location_assignment PIN_46 -to DOUT0[0]
# Sources
set_global_assignment -name VERILOG_FILE ../../altera/countbits.v
set_global_assignment -name VERILOG_FILE ../../altera/packetfifo.v
set_global_assignment -name VERILOG_FILE ../../altera/frontend.v
set_global_assignment -name VERILOG_FILE ../../altera/mega/spififo.v
set_global_assignment -name VERILOG_FILE ../../altera/mega/pll192h.v
set_global_assignment -name VERILOG_FILE ../../altera/mega/fifo8.v
set_global_assignment -name VERILOG_FILE ../../altera/spi_slave.v
set_global_assignment -name VERILOG_FILE ../../altera/conf_reg.v
set_global_assignment -name VERILOG_FILE ../../altera/pll192_test.v
set_global_assignment -name VERILOG_FILE nmahepam.v
set_global_assignment -name VERILOG_FILE stis_ana_core.v
set_global_assignment -name VERILOG_FILE dorn.v
set_global_assignment -name VERILOG_FILE ../../altera/adc128s102.v
set_global_assignment -name VERILOG_FILE dmem.v
set_global_assignment -name VERILOG_FILE divider.v
set_global_assignment -name VERILOG_FILE multiply.v
set_global_assignment -name VERILOG_FILE ../../altera/slow_clock.v
set_global_assignment -name VERILOG_FILE ../../altera/mem.v
set_global_assignment -name VERILOG_FILE ../../altera/itof.v
set_global_assignment -name VERILOG_FILE ../../nm64/altera/nmcounter.v
set_global_assignment -name VERILOG_FILE ../../irena/altera/ms5540c.v
set_global_assignment -name VERILOG_FILE ../../altera/i2c.v
set_global_assignment -name VERILOG_MACRO "TARGET_ALTERA=1"
set_global_assignment -name VERILOG_MACRO "TARGET_10C25=1"
set_global_assignment -name VERILOG_MACRO "CYCLONE10=1"
set_global_assignment -name VERILOG_MACRO "INFERRED_SRAM=1"
set_global_assignment -name VERILOG_MACRO "INFERRED_MULTIPLIER=1"
set_global_assignment -name VERILOG_MACRO "WITH_FULL_L1_CONF"
set_global_assignment -name VERILOG_MACRO "WITH_FULL_L2_CONF"
set_global_assignment -name VERILOG_MACRO "WITH_FULL_L3_CONF"
set_global_assignment -name VERILOG_MACRO "ANA_WITHOUT_SERIALIZER"
set_global_assignment -name VERILOG_MACRO "SPARSE_TRIG_EN"
set_global_assignment -name VERILOG_MACRO "L2_AHEPAM"
set_global_assignment -name VERILOG_MACRO "NMLEIA"

9
dorn/altera/nmleia.sdc Normal file
View file

@ -0,0 +1,9 @@
create_clock -name clk_12 -period 83.333 clk_12
create_clock -name clk_T1 -period 66.667 clk_T1
create_clock -name spi_sck -period 33.333 spi_sck
derive_pll_clocks
derive_clock_uncertainty
set_false_path -from spi_sck -to clk_12
set_false_path -from clk_12 -to spi_sck
set_false_path -from spi_sck -to {pll0|altpll_component|auto_generated|pll1|clk[2]}
set_false_path -from {pll0|altpll_component|auto_generated|pll1|clk[2]} -to spi_sck

135
dorn/altera/nmleia.warnings Normal file
View file

@ -0,0 +1,135 @@
quartus/nmleia.asm.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
quartus/nmleia.asm.rpt:Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
quartus/nmleia.fit.rpt: 21. I/O Assignment Warnings
quartus/nmleia.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
quartus/nmleia.fit.rpt:; I/O Assignment Warnings ;
quartus/nmleia.fit.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
quartus/nmleia.fit.rpt:Warning (15564): Compensate clock of PLL "pll192:pll0|altpll:altpll_component|pll192_altpll:auto_generated|pll1" has been set to clock3
quartus/nmleia.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
quartus/nmleia.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
quartus/nmleia.fit.rpt:Warning (176674): Following 9 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
quartus/nmleia.fit.rpt: Warning (176118): Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
quartus/nmleia.fit.rpt: Warning (176118): Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
quartus/nmleia.fit.rpt: Warning (176118): Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
quartus/nmleia.fit.rpt: Warning (176118): Pin "ARx[3]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[3](n)"
quartus/nmleia.fit.rpt: Warning (176118): Pin "ARx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[2](n)"
quartus/nmleia.fit.rpt: Warning (176118): Pin "ARx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[1](n)"
quartus/nmleia.fit.rpt: Warning (176118): Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
quartus/nmleia.fit.rpt: Warning (176118): Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
quartus/nmleia.fit.rpt: Warning (176118): Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
quartus/nmleia.fit.rpt:Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/nmleia.fit.rpt:Warning (176251): Ignoring some wildcard destinations of fast I/O register assignments
quartus/nmleia.fit.rpt:Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/nmleia.fit.rpt:Warning (169064): Following 4 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
quartus/nmleia.fit.rpt:Info: Quartus Prime Fitter was successful. 0 errors, 18 warnings
quartus/nmleia.map.rpt:; collision ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; bus_active ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; its_me ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; sdone ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; svalid ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; scollision ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; saddr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; sread ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; start_bit ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; stop_bit ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; qs ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; xx_e ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; hi_e ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; slice ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; fpush ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; fdata ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; ctick ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:; fifo_empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/nmleia.map.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
quartus/nmleia.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(…)
quartus/nmleia.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(…)
quartus/nmleia.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(…)
quartus/nmleia.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(…)
quartus/nmleia.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(…)
quartus/nmleia.map.rpt:Warning (10036): Verilog HDL or VHDL warning at nmahepam.v(…): object "pll_clock" assigned a value but never read
quartus/nmleia.map.rpt:Warning (10034): Output port "STx" at nmahepam.v(…) has no driver
quartus/nmleia.map.rpt:Warning (10034): Output port "ADC_nRES" at nmahepam.v(…) has no driver
quartus/nmleia.map.rpt:Warning (10034): Output port "ADC_SDI" at nmahepam.v(…) has no driver
quartus/nmleia.map.rpt:Warning (10034): Output port "ADC_SCK" at nmahepam.v(…) has no driver
quartus/nmleia.map.rpt:Warning (10034): Output port "ADC_nCE" at nmahepam.v(…) has no driver
quartus/nmleia.map.rpt:Warning (10034): Output port "DAC_SDI" at nmahepam.v(…) has no driver
quartus/nmleia.map.rpt:Warning (10034): Output port "DAC_SCK" at nmahepam.v(…) has no driver
quartus/nmleia.map.rpt:Warning (10034): Output port "DAC_nCS" at nmahepam.v(…) has no driver
quartus/nmleia.map.rpt:Warning (10034): Output port "THR_SDI" at nmahepam.v(…) has no driver
quartus/nmleia.map.rpt:Warning (10034): Output port "THR_SCK" at nmahepam.v(…) has no driver
quartus/nmleia.map.rpt:Warning (10034): Output port "THR_nCS" at nmahepam.v(…) has no driver
quartus/nmleia.map.rpt:Warning (10036): Verilog HDL or VHDL warning at stis_ana_core.v(…): object "incr_base" assigned a value but never read
quartus/nmleia.map.rpt:Warning (10036): Verilog HDL or VHDL warning at stis_ana_core.v(…): object "mem_reset" assigned a value but never read
quartus/nmleia.map.rpt:Warning (10036): Verilog HDL or VHDL warning at stis_ana_core.v(…): object "rb_reset" assigned a value but never read
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 16 to match size of target (4)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 16 to match size of target (4)
quartus/nmleia.map.rpt:Warning (10036): Verilog HDL or VHDL warning at dorn.v(…): object "dtrig_en" assigned a value but never read
quartus/nmleia.map.rpt:Warning (10036): Verilog HDL or VHDL warning at dorn.v(…): object "atrig_en" assigned a value but never read
quartus/nmleia.map.rpt:Warning (10036): Verilog HDL or VHDL warning at dorn.v(…): object "sa_triggers" assigned a value but never read
quartus/nmleia.map.rpt:Warning (10036): Verilog HDL or VHDL warning at dorn.v(…): object "adc_valid" assigned a value but never read
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 4 to match size of target (3)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 9 to match size of target (8)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 10 to match size of target (9)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 13 to match size of target (12)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 48 to match size of target (24)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 96 to match size of target (24)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 192 to match size of target (24)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 384 to match size of target (24)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 768 to match size of target (24)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(…): truncated value with size 40 to match size of target (39)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(…): truncated value with size 40 to match size of target (39)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(…): truncated value with size 40 to match size of target (39)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(…): truncated value with size 17 to match size of target (16)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 16 to match size of target (10)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(…): truncated value with size 30 to match size of target (12)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at i2c.v(…): truncated value with size 4 to match size of target (3)
quartus/nmleia.map.rpt:Warning (10230): Verilog HDL assignment warning at i2c.v(…): truncated value with size 4 to match size of target (3)
quartus/nmleia.map.rpt:Warning (12241): 6 hierarchies have connectivity warnings - see the Connectivity Checks report folder
quartus/nmleia.map.rpt:Warning (13039): The following bidirectional pins have no drivers
quartus/nmleia.map.rpt: Warning (13040): bidirectional pin "ATx[2]" has no driver
quartus/nmleia.map.rpt: Warning (13040): bidirectional pin "ATx[1]" has no driver
quartus/nmleia.map.rpt: Warning (13040): bidirectional pin "AIO[6]" has no driver
quartus/nmleia.map.rpt: Warning (13040): bidirectional pin "AIO[5]" has no driver
quartus/nmleia.map.rpt:Warning (13024): Output pins are stuck at VCC or GND
quartus/nmleia.map.rpt: Warning (13410): Pin "STx[4]" is stuck at GND
quartus/nmleia.map.rpt: Warning (13410): Pin "STx[3]" is stuck at GND
quartus/nmleia.map.rpt: Warning (13410): Pin "STx[2]" is stuck at GND
quartus/nmleia.map.rpt: Warning (13410): Pin "STx[1]" is stuck at GND
quartus/nmleia.map.rpt: Warning (13410): Pin "ADC_nRES" is stuck at GND
quartus/nmleia.map.rpt: Warning (13410): Pin "ADC_SDI" is stuck at GND
quartus/nmleia.map.rpt: Warning (13410): Pin "ADC_SCK" is stuck at GND
quartus/nmleia.map.rpt: Warning (13410): Pin "ADC_nCE" is stuck at GND
quartus/nmleia.map.rpt: Warning (13410): Pin "DAC_SDI" is stuck at GND
quartus/nmleia.map.rpt: Warning (13410): Pin "DAC_SCK" is stuck at GND
quartus/nmleia.map.rpt: Warning (13410): Pin "DAC_nCS" is stuck at GND
quartus/nmleia.map.rpt: Warning (13410): Pin "THR_SDI" is stuck at GND
quartus/nmleia.map.rpt: Warning (13410): Pin "THR_SCK" is stuck at GND
quartus/nmleia.map.rpt: Warning (13410): Pin "THR_nCS" is stuck at GND
quartus/nmleia.map.rpt:Warning (15897): PLL "pll192:pll0|altpll:altpll_component|pll192_altpll:auto_generated|pll1" has parameter compensate_clock set to clock0 but port CLK[0] is not connected
quartus/nmleia.map.rpt:Warning (15899): PLL "pll192:pll0|altpll:altpll_component|pll192_altpll:auto_generated|pll1" has parameters clk0_multiply_by and clk0_divide_by specified but port CLK[0] is not connected
quartus/nmleia.map.rpt:Warning (21074): Design contains 22 input pin(s) that do not drive logic
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "clk_T1"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "trigger"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "SRx[4]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "SRx[3]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "SRx[2]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "SRx[1]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "ARx[3]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "ARx[2]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "ARx[1]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "ADC_SDO"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "UNUSED[0]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "UNUSED[1]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "UNUSED[2]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "UNUSED[3]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "UNUSED[4]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "UNUSED[5]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "UNUSED[6]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "UNUSED[7]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "UNUSED[8]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "UNUSED[9]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "UNUSED[10]"
quartus/nmleia.map.rpt: Warning (15610): No output dependent on input pin "UNUSED[11]"
quartus/nmleia.map.rpt:Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 229 warnings
quartus/nmleia.sta.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
quartus/nmleia.sta.rpt:Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning

296
dorn/altera/nmleia_c3.qsf Normal file
View file

@ -0,0 +1,296 @@
# -*- tcl -*-
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# irena_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY quartus
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name TOP_LEVEL_ENTITY nmrena
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:34:07 MäRZ 14, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name MISC_FILE nmrena.dpf
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name CRC_ERROR_CHECKING ON
set_global_assignment -name FORCE_CONFIGURATION_VCCIO OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name EDA_SIMULATION_TOOL "Custom Verilog HDL"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# IRENA
set_instance_assignment -name IO_STANDARD LVDS -to clk_12
set_location_assignment PIN_22 -to clk_12
set_location_assignment PIN_23 -to "clk_12(n)"
set_instance_assignment -name IO_STANDARD LVDS -to clk_T1
set_location_assignment PIN_24 -to clk_T1
set_location_assignment PIN_25 -to "clk_T1(n)"
set_instance_assignment -name IO_STANDARD "2.5 V" -to attn
set_location_assignment PIN_32 -to attn
set_instance_assignment -name IO_STANDARD LVDS -to spi_sck
set_location_assignment PIN_52 -to spi_sck
set_location_assignment PIN_53 -to "spi_sck(n)"
set_instance_assignment -name IO_STANDARD LVDS -to spi_mosi
set_location_assignment PIN_54 -to spi_mosi
set_location_assignment PIN_55 -to "spi_mosi(n)"
set_instance_assignment -name IO_STANDARD LVDS -to spi_miso
set_location_assignment PIN_10 -to spi_miso
set_location_assignment PIN_11 -to "spi_miso(n)"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to spi_miso
set_instance_assignment -name IO_STANDARD LVDS -to trigger
set_location_assignment PIN_129 -to trigger
set_location_assignment PIN_128 -to "trigger(n)"
# Pressure Sensor
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_Dout
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_Din
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_MCLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_SCLK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pt_Din
set_instance_assignment -name FAST_INPUT_REGISTER ON -to pt_Dout
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pt_MCLK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pt_SCLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "8mA" -to pt_Din
set_instance_assignment -name CURRENT_STRENGTH_NEW "8mA" -to pt_MCLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "8mA" -to pt_SCLK
set_instance_assignment -name SLEW_RATE 0 -to pt_Din
set_instance_assignment -name SLEW_RATE 0 -to pt_MCLK
set_instance_assignment -name SLEW_RATE 0 -to pt_SCLK
set_location_assignment PIN_6 -to pt_Dout
set_location_assignment PIN_4 -to pt_Din
set_location_assignment PIN_144 -to pt_MCLK
set_location_assignment PIN_7 -to pt_SCLK
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to pt_Dout
# Serial Ports
set_instance_assignment -name IO_STANDARD "2.5 V" -to SRx
set_instance_assignment -name IO_STANDARD "2.5 V" -to STx
set_location_assignment PIN_136 -to SRx[1]
set_location_assignment PIN_143 -to SRx[2]
set_location_assignment PIN_121 -to SRx[3]
set_location_assignment PIN_135 -to SRx[4]
set_location_assignment PIN_137 -to STx[1]
set_location_assignment PIN_142 -to STx[2]
set_location_assignment PIN_132 -to STx[3]
set_location_assignment PIN_133 -to STx[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SRx
# I2C
set_instance_assignment -name IO_STANDARD LVDS -to ARx
set_instance_assignment -name IO_STANDARD "2.5 V" -to ATx
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ATx
set_instance_assignment -name FAST_INPUT_REGISTER ON -to ATx
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ATx
# LVDS
set_instance_assignment -name IO_STANDARD "2.5 V" -to AIO
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to AIO
set_instance_assignment -name FAST_INPUT_REGISTER ON -to AIO
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to AIO
set_location_assignment PIN_127 -to ARx[1]
set_location_assignment PIN_126 -to "ARx[1](n)"
set_location_assignment PIN_91 -to ARx[2]
set_location_assignment PIN_90 -to "ARx[2](n)"
set_location_assignment PIN_89 -to ARx[3]
set_location_assignment PIN_88 -to "ARx[3](n)"
set_location_assignment PIN_110 -to ATx[1]
set_location_assignment PIN_111 -to ATx[2]
set_location_assignment PIN_112 -to ATx[3]
set_location_assignment PIN_113 -to ATx[4]
set_location_assignment PIN_44 -to AIO[5]
set_location_assignment PIN_46 -to AIO[6]
# set_location_assignment PIN_49 -to AIO[7]
# set_location_assignment PIN_50 -to AIO[8]
# ADC
set_instance_assignment -name IO_STANDARD "2.5 V" -to ADC_nRES
set_instance_assignment -name IO_STANDARD "2.5 V" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "2.5 V" -to ADC_SDO
set_instance_assignment -name IO_STANDARD "2.5 V" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "2.5 V" -to ADC_nCE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ADC_SCK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ADC_nCE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ADC_SDI
set_instance_assignment -name FAST_INPUT_REGISTER ON -to ADC_SDO
set_location_assignment PIN_33 -to ADC_nRES
set_location_assignment PIN_31 -to ADC_SDI
set_location_assignment PIN_43 -to ADC_SDO
set_location_assignment PIN_42 -to ADC_SCK
set_location_assignment PIN_39 -to ADC_nCE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ADC_SDO
# spare pins
# set_instance_assignment -name IO_STANDARD "2.5 V" -to debug
# set_location_assignment PIN_114 -to debug[4]
# set_location_assignment PIN_30 -to debug[5]
# DAC
set_instance_assignment -name IO_STANDARD "2.5 V" -to DAC_nCS
set_instance_assignment -name IO_STANDARD "2.5 V" -to DAC_SCK
set_instance_assignment -name IO_STANDARD "2.5 V" -to DAC_SDI
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DAC_SCK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DAC_nCS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DAC_SDI
set_location_assignment PIN_120 -to DAC_nCS
set_location_assignment PIN_119 -to DAC_SCK
set_location_assignment PIN_115 -to DAC_SDI
# Thresholds DAC
set_instance_assignment -name IO_STANDARD "2.5 V" -to THR_nCS
set_instance_assignment -name IO_STANDARD "2.5 V" -to THR_SCK
set_instance_assignment -name IO_STANDARD "2.5 V" -to THR_SDI
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to THR_SCK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to THR_nCS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to THR_SDI
set_location_assignment PIN_104 -to THR_nCS
set_location_assignment PIN_106 -to THR_SCK
set_location_assignment PIN_105 -to THR_SDI
# Discriminator inputs
set_instance_assignment -name IO_STANDARD "2.5 V" -to SCLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to DIN
set_instance_assignment -name IO_STANDARD "2.5 V" -to nSCLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to nCS
set_instance_assignment -name IO_STANDARD "2.5 V" -to DOUT0
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DOUT0
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SCLK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DIN
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nSCLK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DOUT0
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to UNUSED
set_location_assignment PIN_103 -to UNUSED[0]
set_location_assignment PIN_101 -to UNUSED[1]
set_location_assignment PIN_100 -to UNUSED[2]
set_location_assignment PIN_98 -to UNUSED[3]
set_location_assignment PIN_87 -to UNUSED[4]
set_location_assignment PIN_86 -to UNUSED[5]
set_location_assignment PIN_85 -to UNUSED[6]
set_location_assignment PIN_83 -to UNUSED[7]
set_location_assignment PIN_80 -to UNUSED[8]
set_location_assignment PIN_79 -to UNUSED[9]
set_location_assignment PIN_77 -to UNUSED[10]
set_location_assignment PIN_76 -to UNUSED[11]
set_location_assignment PIN_72 -to nCS[0]
set_location_assignment PIN_71 -to DIN[0]
set_location_assignment PIN_69 -to SCLK[0]
set_location_assignment PIN_68 -to nSCLK[0]
set_location_assignment PIN_67 -to DOUT0[7]
set_location_assignment PIN_66 -to DOUT0[6]
set_location_assignment PIN_65 -to DOUT0[5]
set_location_assignment PIN_64 -to DOUT0[4]
set_location_assignment PIN_60 -to DOUT0[3]
set_location_assignment PIN_59 -to DOUT0[2]
set_location_assignment PIN_58 -to DOUT0[1]
set_location_assignment PIN_51 -to DOUT0[0]
# Sources
set_global_assignment -name VERILOG_FILE ../../altera/countbits.v
set_global_assignment -name VERILOG_FILE ../../altera/packetfifo.v
set_global_assignment -name VERILOG_FILE ../../altera/frontend.v
set_global_assignment -name VERILOG_FILE ../../altera/mega/spififo.v
set_global_assignment -name VERILOG_FILE ../../altera/mega/pll192l.v
set_global_assignment -name VERILOG_FILE ../../altera/mega/fifo8.v
set_global_assignment -name VERILOG_FILE ../../altera/spi_slave.v
set_global_assignment -name VERILOG_FILE ../../altera/conf_reg.v
set_global_assignment -name VERILOG_FILE ../../altera/pll192_test.v
set_global_assignment -name VERILOG_FILE nmahepam.v
set_global_assignment -name VERILOG_FILE stis_ana_core.v
set_global_assignment -name VERILOG_FILE dorn.v
set_global_assignment -name VERILOG_FILE ../../altera/adc128s102.v
set_global_assignment -name VERILOG_FILE dmem.v
set_global_assignment -name VERILOG_FILE divider.v
set_global_assignment -name VERILOG_FILE multiply.v
set_global_assignment -name VERILOG_FILE ../../altera/slow_clock.v
set_global_assignment -name VERILOG_FILE ../../altera/mem.v
set_global_assignment -name VERILOG_FILE ../../altera/itof.v
set_global_assignment -name VERILOG_FILE ../../nm64/altera/nmcounter.v
set_global_assignment -name VERILOG_FILE ../../irena/altera/ms5540c.v
set_global_assignment -name VERILOG_FILE ../../altera/i2c.v
set_global_assignment -name VERILOG_MACRO "TARGET_ALTERA=1"
set_global_assignment -name VERILOG_MACRO "INFERRED_SRAM=1"
set_global_assignment -name VERILOG_MACRO "INFERRED_MULTIPLIER=1"
set_global_assignment -name VERILOG_MACRO "WITH_FULL_L1_CONF"
set_global_assignment -name VERILOG_MACRO "WITH_FULL_L2_CONF"
set_global_assignment -name VERILOG_MACRO "WITH_FULL_L3_CONF"
set_global_assignment -name VERILOG_MACRO "ANA_WITHOUT_SERIALIZER"
set_global_assignment -name VERILOG_MACRO "SPARSE_TRIG_EN"
set_global_assignment -name VERILOG_MACRO "L2_AHEPAM"
set_global_assignment -name VERILOG_MACRO "NMLEIA"

11
dorn/altera/stis_ana_core.v
View file

@ -375,11 +375,16 @@ module stis_ana_core
assign rri[0] = read_fifos;
assign rri[1] = rro[0];
assign rri[3:2] = rro[SLICES*3-1:SLICES*3-2];
assign rri[SLICES*3:4] = rro[SLICES*3-3:1];
assign rbi[SLICES*3] = 0;
assign rbi[SLICES*3-1:SLICES*3-2] = rbo[3:2];
assign rbi[SLICES*3-3:1] = rbo[SLICES*3:4];
assign rbi[0] = rbo[1];
generate
if (SLICES>1)
begin:rrr
assign rri[SLICES*3:4] = rro[SLICES*3-3:1];
assign rbi[SLICES*3-3:1] = rbo[SLICES*3:4];
end
endgenerate
wire [3:0] trigger;
generate
@ -402,7 +407,7 @@ module stis_ana_core
assign sc_incr[SLICES] = 0;
`endif
parameter NHIT1 = 25;
parameter NHIT1 = 3*ND + 1;
parameter NHIT = SLICES*NHIT1;
generate
for (i=0; i<SLICES; i=i+1)

10
irena/altera/Makefile
View file

@ -76,6 +76,16 @@ $(QDIR)/irenacore.rbf: irena.v countbits.v ms5540c.v nmcounter.v \
irena_core.v sfilter.v itof.v \
sram.v sram1024x32.v pll96.v mul13x13.v
irenacore2thr.qpf irenacore2thr.qsf irenacore2thr.sdc: irenacore2thr.%: irenacore.%
cp -v $< $@
$(QDIR)/irenacore2thr.rbf: irena.v countbits.v ms5540c.v nmcounter.v \
direna.v adccntl.v filter.v \
irena_core.v sfilter.v itof.v \
sram.v sram1024x32.v pll96.v mul13x13.v
irenacore2thr_MAPDEFS = TWOTHR=1
irena48.qpf irena48.qsf irena48.sdc: irena48.%: irenacore.%
cp -v $< $@

76
irena/altera/irena.v
View file

@ -141,9 +141,10 @@ module irena
`endif // `ifdef DIRENACORE
`ifdef IRENACORE
wire tick;
`ifndef TWOTHR
irenacore #(.NCH(18), .NT(6), .NX(5)) irena
(.clk96(mclk), .resets(resets[2:0]), .enable(global_enable),
.adc_ce(adc_cs), .adc_clk(adc_sclk), .adc_data(adc_sdata),
@ -163,7 +164,80 @@ module irena
assign fsiz[3] = 15; // 18 channels -> 16 words, 24-bit timestamp
assign fhma[4] = 'h ffff;
`else // !`ifndef TWOTHR
wire [8:0] a_sdata, a_sclk, a_cs;
assign a_sdata[0] = adc_sdata[ 1];
assign a_sdata[1] = adc_sdata[ 2];
assign a_sdata[2] = adc_sdata[ 5];
assign a_sdata[3] = adc_sdata[ 6];
assign a_sdata[4] = adc_sdata[ 9];
assign a_sdata[5] = adc_sdata[10];
assign a_sdata[6] = adc_sdata[13];
assign a_sdata[7] = adc_sdata[14];
assign a_sdata[8] = adc_sdata[17];
assign adc_sclk[ 1] = a_sclk[0];
assign adc_sclk[ 2] = a_sclk[1];
assign adc_sclk[ 5] = a_sclk[2];
assign adc_sclk[ 6] = a_sclk[3];
assign adc_sclk[ 9] = a_sclk[4];
assign adc_sclk[10] = a_sclk[5];
assign adc_sclk[13] = a_sclk[6];
assign adc_sclk[14] = a_sclk[7];
assign adc_sclk[17] = a_sclk[8];
assign adc_sclk[ 0] = 0;
assign adc_sclk[ 3] = 0;
assign adc_sclk[ 4] = 0;
assign adc_sclk[ 7] = 0;
assign adc_sclk[ 8] = 0;
assign adc_sclk[11] = 0;
assign adc_sclk[12] = 0;
assign adc_sclk[15] = 0;
assign adc_sclk[16] = 0;
assign adc_cs[ 1] = a_cs[0];
assign adc_cs[ 2] = a_cs[1];
assign adc_cs[ 5] = a_cs[2];
assign adc_cs[ 6] = a_cs[3];
assign adc_cs[ 9] = a_cs[4];
assign adc_cs[10] = a_cs[5];
assign adc_cs[13] = a_cs[6];
assign adc_cs[14] = a_cs[7];
assign adc_cs[17] = a_cs[8];
assign adc_cs[ 0] = 1;
assign adc_cs[ 3] = 1;
assign adc_cs[ 4] = 1;
assign adc_cs[ 7] = 1;
assign adc_cs[ 8] = 1;
assign adc_cs[11] = 1;
assign adc_cs[12] = 1;
assign adc_cs[15] = 1;
assign adc_cs[16] = 1;
irenacore #(.NCH(9), .NT(6), .NX(5)) irena
(.clk96(mclk), .resets(resets[2:0]), .enable(global_enable),
.adc_ce(a_cs), .adc_clk(a_sclk), .adc_data(a_sdata),
.we(we), .wp(wp), .wa(wa), .wd(wd), .re(re), .rd(rd),
.go(tick), .clock(clock),
.fifo_push(fifo_push[4:2]), .fifo_full(fifo_full[4:2]),
.fifo1(fifo[2]), .fifo2(fifo[3]),
.fsiz1(fsiz[2]), .fmatch1(ev_size_match),
.fifo3(fifo[4]), .fsiz3(fsiz[4]), .fhva3(fhva[4]),
.trig() );
assign fhma[2] = 'h ffff;
assign fhva[2] = 'h beef;
assign fhma[3] = 'h ffff;
assign fhva[3] = 'h 5a61;
assign fsiz[3] = 15; // 18 channels -> 16 words, 24-bit timestamp
assign fhma[4] = 'h ffff;
`endif
`endif
frontend front