Stephan/solo_altera
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  • ad05c88318 shaper2u2 ??? stephan 2015-01-10 15:02:08 +00:00
  • b2a59d0803 heteptana changelog stephan 2015-01-10 15:00:46 +00:00
  • 15060cf682 add missing import stephan 2015-01-09 20:48:40 +00:00
  • f6e1fd81a5 rpigse: fix python indent and syntax ??? stephan 2015-01-09 20:12:19 +00:00
  • 3ca4b6f786 hetept_ppss: make executable stephan 2015-01-09 14:30:51 +00:00
  • 37b92c07d7 sologse: remove bogus import line stephan 2015-01-09 13:09:21 +00:00
  • d1a5abbe32 solomsg: use new solomsgclass stephan 2015-01-09 12:05:57 +00:00
  • c041e6554e idata: gnuplot syntax stephan 2015-01-09 12:05:35 +00:00
  • dbe0f07f3f pidata: gnuplot 5 syntax stephan 2015-01-09 12:05:06 +00:00
  • 35956f301f hetept data: use mV from coeff A stephan 2015-01-09 12:04:23 +00:00
  • 116cb10845 itf_parser.c: Updated STEP parser code. terasa 2015-01-09 11:26:50 +00:00
  • cf9d08bd3e memtest.*: Added memtest L3 code. terasa 2015-01-09 10:10:35 +00:00
  • a5df3a4941 corrected msg() functionality grunau 2015-01-09 09:59:20 +00:00
  • 9b1f5033fe Added dps_test.py, several changes in dps_table for additional functionality grunau 2015-01-09 09:21:52 +00:00
  • fa13caf0f4 step.gtkw: cleaned up wetzel 2015-01-08 19:54:35 +00:00
  • 73925fd83c stein/em/v01: Updated contraints and project files. kruse 2015-01-08 16:02:54 +00:00
  • d7727e70a3 stein/em: Added synthesis log step.srr kruse 2015-01-08 15:34:08 +00:00
  • 980f6a0758 Copied Verilog code to em/v01 and adapted project paths. kruse 2015-01-08 15:26:19 +00:00
  • f5242c2177 stein_ix_controller: added syn_preserve directives wetzel 2015-01-08 14:00:04 +00:00
  • 2eba9a4c5c step: connected EEPROM_nBUSY wetzel 2015-01-08 13:36:11 +00:00
  • bb727059ef step: connected EEPROM_nBUSY wetzel 2015-01-08 13:35:48 +00:00
  • 32bda6b8af solomsg.py: Updated read_histogram code to make better use of EDACdecoder. terasa 2015-01-08 09:53:28 +00:00
  • c79752f7b7 l3pipe.py: Removed pipe subdirectory and moved contents to l3 directory. terasa 2015-01-08 09:16:14 +00:00
  • 298fc31723 hamming: add 32-bit python implementation stephan 2015-01-07 22:48:03 +00:00
  • a15913accd ppss_table: tagged msgs, ... stephan 2015-01-07 21:08:55 +00:00
  • 231013754d i128event.py: Added generic PHA event to process arbitrary data. l3test.l3,l3test.dat: Added L3 opcode test code. terasa 2015-01-07 16:35:37 +00:00
  • ecfd4dc629 EDACdecoder.py: now raises ValueError for incorrect EDAC boden 2015-01-07 15:24:51 +00:00
  • 066b32269e solomsg.py: Added Sebastian's EDACdecoder. terasa 2015-01-07 15:19:39 +00:00
  • d13a75072e heteptdig em/v06 - QM: separate SDC for synthesis layout SDC fixes final ? bitfile for QM stephan 2015-01-07 10:12:37 +00:00
  • 2e9ab722de ppss_table: can load a small table :-) stephan 2015-01-06 15:49:47 +00:00
  • 402186633e EDACdecoder.py: fixed code for 0th parity bit boden 2015-01-06 11:16:32 +00:00
  • 678a901050 EDACdecoder.py: small changes boden 2015-01-06 09:41:26 +00:00
  • 9d3ef849f0 EDACdecoder.py: functions for en- and decoding EDAC-values boden 2015-01-05 17:25:05 +00:00
  • 4f0d9fdb20 heteptdig em/v06: copy sdc for synthesis mods stephan 2015-01-05 12:01:09 +00:00
  • ad18c9b164 heteptana em/v04: AX2000 BGA burned stephan 2014-12-17 15:06:22 +00:00
  • 51eb0453f2 pipe.py: Reverted changes by rasch, and copied changes to pipe_rasch.py. Please only check in tested and working code which not breaks previous functionality. terasa 2014-12-16 17:17:01 +00:00
  • 1c883d5d19 i128event.py: Ignore TRUNCATED packets in step PHA data. terasa 2014-12-16 17:03:29 +00:00
  • 7db1d7c883 ixrc.py: Bugfix. terasa 2014-12-16 15:11:52 +00:00
  • d05dcf91dd solomsg.py: Inject data even when no trigger-class filter is given. terasa 2014-12-16 15:10:23 +00:00
  • 1f35e822c0 i128event.py: Added step_pha. terasa 2014-12-16 15:08:36 +00:00
  • 3198b30d7c heteptdig/em/v06: add: aldec/heteptdig_flashpro4 burned into EM1 stephan 2014-12-16 12:22:41 +00:00
  • 7d1d29de78 heteptdig em/v06: synthesis for EM1 with MEM16EE on Aldec prototype stephan 2014-12-16 11:33:54 +00:00
  • df7d4844f1 heteptdig em/v06: aldec constraints SDC same as RTAX with fixed driver instances PDC with unused pins, so that those do not end up in collision with the adapter IOS with high level on SRAM/EEPROM nCE The designer will throw out RAM_D registers, ignore those warnings stephan 2014-12-15 12:40:41 +00:00
  • 95bbace22e heteptdig em/v06: version ID 'h F6 stephan 2014-12-15 12:33:42 +00:00
  • 5d43708f77 ppss_table.py: Added basic multiitem support. terasa 2014-12-12 22:04:25 +00:00
  • da669dc883 heteptdig em/v06: synthesis and layout for RTAX with a fix in pha.v to not infer a RAM block all new SDC file with generated mclk all SRAM outputs FAST stephan 2014-12-12 20:04:36 +00:00
  • 686bc7e2d7 heteptana em/v04: copy of the verilig cell lib from libero 9.2 this is just empty moules, no simulation lib stephan 2014-12-12 14:10:18 +00:00
  • 9ddaa70370 steinrc.py: Updated get_hk() function to match datasheet. terasa 2014-12-12 13:51:25 +00:00
  • 66c49ee340 heteptana em/v04: layout 25 iteration (non-incremental) nobch 1 iteration stephan 2014-12-12 13:45:15 +00:00
  • 5b920ac4aa steingse.py: Added offset option to threshold optimizer. terasa 2014-12-12 12:20:20 +00:00
  • f97d5a9989 steingse.py: Better defaults and safety for too low or high thresholds. terasa 2014-12-11 16:19:00 +00:00
  • 991d232cf2 heteptana em/v04: adc schedule Add sclknn registers for direct posedge -> negedge path replicated for each SCLK output. TODO: at resync high, CLKDIV=3, there is a spurious SCLK glitch after CS is deasserted. TODO: ckeck with CLKDIV=6 stephan 2014-12-11 15:58:06 +00:00
  • d9a247c85d steingse.py: Added tool to determine optimal thresholds for Idefixen. terasa 2014-12-11 15:55:24 +00:00
  • 04ddd1fa55 heteptdig em/v06: new synthesis, with an inferred RAM that is not SEU safe stephan 2014-12-11 13:43:33 +00:00
  • 58d0228308 ixrc.py: Adapted temperature readout code. terasa 2014-12-11 11:37:00 +00:00
  • 76efe1d429 heteptdif em/v06: update sdc file clock uncerteainty to model Xtal duty cycle ?? more or less complete IO contraints clock phases stephan 2014-12-10 22:41:58 +00:00
  • a1c8c277b2 heteptdig em/v06: add syn_preserve to IO registers stephan 2014-12-10 22:39:53 +00:00
  • 41d63828c2 heteptana: merge -c 3599,3602 from em/v04 stephan 2014-12-10 20:09:43 +00:00
  • a41b1a2312 heteptana em/v04: add syn_preserve to input registers, so they will not be replicated for fanout fix declaration after use full constrain IO timing add clock uncertainty, will this cover dutycycle uncertainty? add NO_BCHANNEL netlist stephan 2014-12-10 16:08:30 +00:00
  • c58d90f8f5 heteptana em/v04 synthesis: again with Libero 9.2 stephan 2014-12-09 16:14:31 +00:00
  • 44f21417f7 heteptana em/vo4 synthesis with synopsys from libero 9.1 stephan 2014-12-09 15:54:12 +00:00
  • f2e0003f78 heteptana em/v04: synthesis: delare reg before use stephan 2014-12-09 12:39:09 +00:00
  • bc3fbd847d heteptana em/v04: synthesis with libero 9.2 version of synopsis: G-2012.09A-SP4 stephan 2014-12-09 12:25:46 +00:00
  • bebd2827ec heteptana em/v04: fix Makefile for sim of actel.v stephan 2014-12-09 11:51:28 +00:00
  • 2e061129e4 pipe.py: Reverted changes by rasch, and copied changes to pipe_rasch.py. Please only check in tested and working code, which does not break previous functionality. terasa 2014-12-08 19:47:30 +00:00
  • ea7e1216fc heteptdig em/v06: merge -c 3548,3592-3593 Use two words in pha.pha_acc_mem for wptr and tcnt. This allows to use the full 24 bits for tcnt in the PHA buffers. stephan 2014-12-08 08:19:52 +00:00
  • 18a5f147c8 pha: remove obsolete TODO comment stephan 2014-12-08 08:16:37 +00:00
  • 667bc29959 pha: Use only one RAM block for pha_acc_mem. The SUE of the removed RAM block causes different PRNG sequences for the analog input data. Also: pass -v to vvp. stephan 2014-12-07 19:25:37 +00:00
  • bf99b86424 pha: Use separate memory in pha_acc_mem for tcnt and wptr. This allows for 24 bit tcnt without an extra RAM block. The extra RAM block is still there, not to mess up the PRNG. The next commit will have the extra RAM removed and a new gold file. stephan 2014-12-07 15:47:13 +00:00
  • e0fb0e2176 heteptana: merge -c 3578 stephan 2014-12-06 15:13:58 +00:00
  • ffc966c6c8 heteptana/em/v04: remove a reference to v03 stephan 2014-12-05 13:58:40 +00:00
  • 9fc7249fd1 ... wetzel 2014-12-05 12:57:43 +00:00
  • fc11b6d5ef icu-message.txt: added assignment to conf bits for Step l1 config wetzel 2014-12-05 12:57:29 +00:00
  • c5bd9940e5 step: changed assignment of bits in l1/l2 config wetzel 2014-12-05 12:56:38 +00:00
  • aff27ae183 heteptdig em/v06: merge various fixes and cleanups pha reset and enables initial statements (not supported for ACTEL target) comments stephan 2014-12-04 16:13:07 +00:00
  • 8c7c6b2e81 heteptdig: add actel.v lib to Makefile stephan 2014-12-04 16:09:43 +00:00
  • 036e4e0559 solomsg: MSG0 enables reassignment stephan 2014-12-04 16:08:45 +00:00
  • 3f76ea93b5 ppss_table.py: Added some typechecks and exception handling. terasa 2014-12-04 14:58:47 +00:00
  • 5c8eda23f0 ppss_table.py: Initial commit of python ppss_table creator. terasa 2014-12-04 14:49:00 +00:00
  • 2f949071eb changed slew rates of non LVPECL signals connected to the IdeF-X from High to Low signals are: SC and STROBEn kruse 2014-12-04 14:32:00 +00:00
  • 3bf27459c2 itf_parser.c: Added tabstop for Moritz. wetzel 2014-12-04 14:15:05 +00:00
  • 10e8e5dac5 heteptdig em/v06: copy actel.v again stephan 2014-12-04 11:01:50 +00:00
  • 583df692db heteptana em/v04: remove iopad models from toplevel file, use library instead stephan 2014-12-04 10:57:51 +00:00
  • 13d8d2f942 actel.v: move one directory down stephan 2014-12-04 10:57:12 +00:00
  • 3c32880b12 heteptana em/v04: copy actel.v stephan 2014-12-04 10:52:41 +00:00
  • f308a7679a steinrc.py: Changed read_delay calculation to use ceil instead of normal rounding. Use TEMP sensor on DIGITAL board. terasa 2014-12-03 11:22:10 +00:00
  • 994da61de7 itf_parser.c: removed whitespace in formatting. terasa 2014-12-03 11:20:36 +00:00
  • 1f03317a7e step low speed stream: added gab between last put and submit wetzel 2014-12-02 13:01:05 +00:00
  • 432db47693 actel sim models: created file for actel specific sim models wetzel 2014-12-02 12:15:01 +00:00
  • b04721fc76 step/Makefile: moved CLK- and LVPECL-Buffer to actel.v wetzel 2014-12-02 12:14:20 +00:00
  • 374c5b0519 step: changed name of EEPROM_BUSY to EEPROM_nBUSY wetzel 2014-12-02 11:31:14 +00:00
  • 6bca43827f stein_ix: fix baseline bit in stream data stephan 2014-11-28 18:58:13 +00:00
  • 61accc3423 rpigse: Add fifo header mask registers in the FPGA. Add python functions to configure FIFOs and routing. stephan 2014-11-28 18:45:59 +00:00
  • 77032048b9 packetfifo: fix match validation timing for the mask match case, the validation is not normally required stephan 2014-11-28 18:44:39 +00:00
  • 9423483f02 ixrc.py: Removed read code in setters. Default values for threshholds is 63 for thresholds and 0 for everything else. panitzsch 2014-11-28 15:12:57 +00:00
  • 595a2f8a34 itf_parser.c: step_event: data should be integer, and updated description. terasa 2014-11-28 14:09:17 +00:00
  • 1a56092a4a itf_parser.c: Added hexdump function, reworked STEP parser. terasa 2014-11-28 13:13:23 +00:00
  • c3f5e2ff54 rpigse: add routing() and packetfifo_config() stephan 2014-11-28 11:14:29 +00:00
  • 3dbb0a6e2e step: reverted some changes and fixed wrong namings wetzel 2014-11-28 10:11:17 +00:00
  • 108ff316a4 stein: fix ttf_len stephan 2014-11-28 09:30:00 +00:00