Stephan/solo_altera
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  • 9c641365d8 stein: lss and hss fixes stephan 2014-11-27 23:59:22 +00:00
  • 70b9cc32d7 heteptdig: gold with initials stephan 2014-11-27 22:58:34 +00:00
  • a1989161df backend+: Review power on reset. Add initial statements for synthesis, in case the target supports a define power on state. stephan 2014-11-27 20:50:02 +00:00
  • 5788d21217 step.v: Adapted number of unused pins. kruse 2014-11-27 14:19:37 +00:00
  • 22ecfbdadb stein/em: Deleted old aldec flash folder. kruse 2014-11-27 14:16:57 +00:00
  • 9612e7ef0c stein/em: Added flash folder. kruse 2014-11-27 14:16:10 +00:00
  • 61f41d810b pha: New reset: e_reset = strobes[6] Restore orthogonal meanings to e_enable, l3_enable, pha_enable. Do not clear events at ~e_enable. Events will be processed when ~e_enable. Do not clear events at ~l3_enable. Events can be stored without processing them immediately. stephan 2014-11-27 11:27:51 +00:00
  • ec2c4209aa heteptdig: all new gold, the extra RAM unsettled the PRNG stephan 2014-11-26 16:29:01 +00:00
  • 992e71d7fc stein/libero: Adapted project file paths to local paths instead of network shares. kruse 2014-11-26 13:24:38 +00:00
  • fd40691d09 step.pdc/step.sdc: Adopted pinlist to verilog code. Commented timing constraints. kruse 2014-11-26 13:22:00 +00:00
  • 2d2fdbd6cd step.v: EEPROM_nBUSY is not assigned to UNUSED anymore kruse 2014-11-26 13:17:10 +00:00
  • d6355a7d14 heteptdig: more enables reassignment sim fixes stephan 2014-11-26 13:07:02 +00:00
  • e57d5ae341 pha: 24-bit pha counters, uses one more RAM block stephan 2014-11-26 13:05:51 +00:00
  • 6cc920bf10 heteptcore: remode a fixed TODO stephan 2014-11-26 12:56:42 +00:00
  • 4180cdc3aa heteptdig: reduce SEU_RATE to avoid double bit errors in the PPSS stephan 2014-11-26 12:55:43 +00:00
  • e3ff86c809 sologse: implement solo.atbrk() and gsecmd() stephan 2014-11-26 12:54:16 +00:00
  • f8f0291673 stein/em: Added step_aldec flash project. kruse 2014-11-26 11:55:27 +00:00
  • 79bb514dbd em: Created folder structure to include libero project files and constraints. kruse 2014-11-26 11:25:28 +00:00
  • 6537416e41 step.v: Adapted number of UNUSED pins and assigned nBUSY to UNUSED. kruse 2014-11-26 11:14:57 +00:00
  • dc5592f40b merge -c 3540: fallout from enables reassignment stephan 2014-11-25 12:25:48 +00:00
  • 87f7dcdf38 heteptdig em/v06: simulate new enables/confs assignments stephan 2014-11-25 11:31:50 +00:00
  • 4ee3865932 step.v: Added another wire to TRIG inversion. kruse 2014-11-24 17:17:48 +00:00
  • 48f9f1bfeb stein_core.v: Moved conf registers further to top. (Define before use!) kruse 2014-11-24 14:48:22 +00:00
  • 60a08b5df5 stein_core.v: Moved wires to allow compilation with Libero toolchain. step.v: Adapted number of UNUSED pins (27->30). kruse 2014-11-24 11:04:24 +00:00
  • 23cdee284a itf_paser.c: Added step_event function to parse STEP ITF events. terasa 2014-11-24 10:15:56 +00:00
  • d4c0b535f9 steinrc.py: Added new STEP acquire and stream enables/disables. terasa 2014-11-24 09:15:29 +00:00
  • 8c9986a5e6 heteptdig em/v06: merge -c 3375 stephan 2014-11-24 08:46:19 +00:00
  • 5b5c146c0e heteptdig em/v06: merge -c 3518: rearrange enables and confs stephan 2014-11-24 08:43:39 +00:00
  • 424902d9c9 heteptdig em/v06: merge -c 3508: initialize enables and confs stephan 2014-11-24 08:42:00 +00:00
  • 4481eafdcb heteptdig em/v06: merge -c 3507: drive EEPROM_nRES from confs[7] stephan 2014-11-24 08:40:22 +00:00
  • da47d7a68a stein_core: fixed a bug (tff_data got the wrong signal) and did some cosmetics wetzel 2014-11-21 22:47:34 +00:00
  • 1b7732ad5a acquire: removed sync word low speed stream and made sure there are at least 4clk cycles (48 MHz, configurable) between each lss_put wetzel 2014-11-21 22:46:38 +00:00
  • 553de0e548 step.gtkw: added signals for streaming tests wetzel 2014-11-21 22:44:56 +00:00
  • daeac2a0cf makefile: added flag for streaming to acquire sim wetzel 2014-11-21 22:44:10 +00:00
  • b657e1e578 step: reworked the production way of low speed streaming data wetzel 2014-11-21 18:41:43 +00:00
  • 41e042785f ... wetzel 2014-11-21 18:37:32 +00:00
  • b84886fd10 frontend: fixed a bug (width of s_data) wetzel 2014-11-21 13:20:06 +00:00
  • d9138319cd acquire: added module number to the data wetzel 2014-11-21 13:19:09 +00:00
  • 8ce1cb152b stein_core: made acquire modules enable seperately wetzel 2014-11-21 13:02:30 +00:00
  • e673a06b66 icu-message/ enables: swapped order of IXs in enables wetzel 2014-11-21 13:00:32 +00:00
  • 2e8b882ea0 heteptcore: reassign confs and enable bits to accomodate STEP stephan 2014-11-21 12:49:31 +00:00
  • ec6878f2fd heteptdig em/v06: merge -c 3390: ACTEL LVPECL and HCLK driver models stephan 2014-11-21 12:46:27 +00:00
  • 60002ef8f8 heteptdig em/v06: support sim of mem16ee driver stephan 2014-11-21 12:45:02 +00:00
  • 2f112c58bc ... wetzel 2014-11-21 11:27:21 +00:00
  • 83f8471751 Makefile/step: added flag for high speed streaming wetzel 2014-11-21 11:27:00 +00:00
  • 7ab3c744d5 heteptdig em/v06: merge memasync16ee rework for fully registered ports. stephan 2014-11-20 17:06:17 +00:00
  • 222d214cea heteptdig em/v06: branched from em/v05 stephan 2014-11-20 16:45:09 +00:00
  • d7f505efb5 heteptana em/v04: merge -c 3402,3505: aschedule change related to STEP and fallout stephan 2014-11-20 16:30:43 +00:00
  • 00cb4950f1 backend: use initial statement to clear confs and enables at startup stephan 2014-11-20 13:46:50 +00:00
  • b08668b407 backend: Provide a confs port all the way to the toplevel. Use confs[7] to drive EEPROM_nRES. stephan 2014-11-20 13:46:08 +00:00
  • e88dd76889 TODO pha: check l3_enable and pha_enable logic stephan 2014-11-20 13:44:03 +00:00
  • 489b7ad48e heteptana hkadc: A change in module aschedule for STEP broke heteptana hkadc. The change suppressed din1 and doute strobes when the ADC is not active. This had two effects: 1. The hkadc state machine would hang at startup. 2. The state machine would not terminate reading the sequence. This was fixed by driving the state from mtick, and fix the resulting timing shifts. The result is a more robust design of the hkadc module. stephan 2014-11-20 13:42:59 +00:00
  • d0664a580f PQM preamps: add hetpreamps data stephan 2014-11-20 13:38:07 +00:00
  • c7724a917e irena/data Makefile: remove irenaevents.py from .E target stephan 2014-11-20 13:36:52 +00:00
  • 328d0192ca idata: drop order 3 poly fits to order 1 polynom, i.e, linear stephan 2014-11-20 13:35:52 +00:00
  • 819c6e79c2 idata: update README stephan 2014-11-20 13:34:19 +00:00
  • 14c59f9046 itf_parser.c: missing adc values are now 'x' not '0' in STEIN parser. terasa 2014-11-19 12:43:03 +00:00
  • 7d221d7902 steingse.py: Made executable. For real now. terasa 2014-11-19 10:12:42 +00:00
  • 81b7f77143 steingse.py: Made executable. terasa 2014-11-19 10:12:02 +00:00
  • b210937474 steingse.py: Removed pointless imports and commands. terasa 2014-11-19 09:56:18 +00:00
  • 1df6886886 Added STEIN and IDE-fx helper code. terasa 2014-11-19 09:52:38 +00:00
  • 6ab2085190 idef-x-rc.py: Updated to latest version from git. terasa 2014-11-19 09:49:50 +00:00
  • 52a336c226 step: Inverted TRIG[1] and READ[1] in test jig according to board layout wetzel 2014-11-18 22:04:19 +00:00
  • 74e37d87f9 l3trigger.tex: added information about compare_l3_pha.py boden 2014-11-18 16:54:42 +00:00
  • f1a5458969 compare_l3_pha.py: new version with new options and reduced memory usage for big .itf files, also implemented l3 log function boden 2014-11-18 16:53:18 +00:00
  • ea9e9d56bc step.v: Swapped inversion on TRIG due to swap of TRIG signals on flexboard: /home/asterix/solo/STEIN/idef-x/v04/idef-x_sch.pdf terasa 2014-11-18 11:22:38 +00:00
  • 8ad9af5439 solomsg.py: Added clear_histogram. terasa 2014-11-17 14:47:47 +00:00
  • 3e525fdf3f First try at pipe.py and dps-simulator rasch 2014-11-17 14:46:47 +00:00
  • 253ee56478 step:... wetzel 2014-11-13 16:37:34 +00:00
  • 3bf054ae3d step*.l3: Further testing. terasa 2014-11-13 16:08:19 +00:00
  • b18471bd93 step: updatet dimension of ADC interface signals, swapped TRIG[2] and READ[1] to adapt to board layout, removed second OH_PWM pin wetzel 2014-11-13 15:54:52 +00:00
  • bfc070a8a3 l3sim: enforce numbers in regs[] to be 29 bits stephan 2014-11-13 15:01:56 +00:00
  • 1de66d7b5a l3sim: add sign extension to x arg of ADDI stephan 2014-11-13 14:43:48 +00:00
  • c5eff67abb step: updated amount of unused pins wetzel 2014-11-13 13:49:26 +00:00
  • f313cfff1e step: updated to correct RAM sim models, fixed a bug (missing clk) wetzel 2014-11-13 13:47:58 +00:00
  • f1c83f6979 pipe.py: Added more commandline options: -v: verbosity of l3 sim, -n: number of phas to inject, -a: numpy array output instead of raw binary. terasa 2014-11-13 13:45:37 +00:00
  • 6fa5b604d0 step: updated amount of unused pins wetzel 2014-11-13 13:16:15 +00:00
  • 48b1143125 step: updated RAM sim models to step wetzel 2014-11-13 13:14:23 +00:00
  • 1a6a1f1fb0 step: updated interface wetzel 2014-11-12 14:50:48 +00:00
  • 6ae80a80fa hetpreamps: NCR (-0005 ?): partslist was wrong for RH5, RH8, RL8. RH5 still had the old 750Ω instead of 845Ω. RH8 and RL8 were never properly configured. New values: RH5, RL5 = 845Ω_1% RL8 = none RH5 was fixed in the PQM production partslist by Mahesh. R[HL]8 were populated with the wrong parts. stephan 2014-11-12 13:23:02 +00:00
  • 5ff80ec72f bf862: screening data: regression Vgs Idd, green selects good parts stephan 2014-11-11 20:46:33 +00:00
  • 9dfab37d40 bf862: screening data from PDF into pspreadsheet stephan 2014-11-11 20:15:41 +00:00
  • 8d9afb7852 l3trigger.tex: Added citations. Moved DPS subscetion to new 'Utilities' section terasa 2014-11-11 14:34:06 +00:00
  • 1699fa49d0 step: clks may not lead to regs in actel compiler wetzel 2014-11-11 12:19:42 +00:00
  • 697b11fbc9 step: changed position of reg declaration (actel compiler) wetzel 2014-11-11 11:39:03 +00:00
  • 825de23733 step: changed position of reg declaration (actel compiler) wetzel 2014-11-11 11:35:32 +00:00
  • 80168e1c63 acquire: fixed a bug (= to <=) wetzel 2014-11-11 11:33:28 +00:00
  • 69f135c3d1 acquire: changed position of reg declaration (actel compiler) wetzel 2014-11-11 11:29:14 +00:00
  • 1b13e747ba l3trigger.tex: Refined some sections. terasa 2014-11-11 11:17:56 +00:00
  • 6af3526283 solomsg.py: Added unpack_edac helper function. terasa 2014-11-10 16:30:24 +00:00
  • 94501da8ed l3trigger.tex: Added references. terasa 2014-11-10 15:54:35 +00:00
  • 434d479384 l3trigger.tex: edited section about DPS, dps_table.py: binary flag for files included, standard output now stdout instead of stderr grunau 2014-11-10 15:26:41 +00:00
  • c8c262c484 dps_table.py: Bugfix; l3trigger.tex: initial section release for DPS grunau 2014-11-10 14:16:09 +00:00
  • 18cefbab25 l3trigger.tex: initial commit grunau 2014-11-10 13:53:52 +00:00
  • 40d209d05f Bugfix grunau 2014-11-10 13:36:28 +00:00
  • 5926fd5503 dps_table.py: shifted dps configuration in external files; added documentation folder /sirena/altera/doc/ for latex documentation grunau 2014-11-10 13:34:42 +00:00
  • 856847ca4d solomsg.py: Bugfix terasa 2014-11-07 10:36:40 +00:00
  • 23d77f521b solomsg.py: Added option to only inject given trigger classes. terasa 2014-11-07 10:34:19 +00:00
  • dcd72cbb22 ept_simple.l3: added support for all trigger classes boden 2014-11-07 10:33:32 +00:00
  • 8ba4b11d16 solomsg.py: Bugfix of injector. terasa 2014-11-07 09:46:22 +00:00