Stephan/solo_altera
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  • 67c36ffdfb heteptdig: gtkw for mem16ee stephan 2014-10-23 13:30:07 +00:00
  • a355a14e97 memport: fully pad-registered IO in memasync16ee24 stephan 2014-10-22 23:15:28 +00:00
  • b4c6f30cf9 heteptdig: merge -c 2651 MEM16EE sim fix into trunc stephan 2014-10-22 21:06:07 +00:00
  • 76cdbe2169 memport: remove unmaintained non-ee versions of sran drivers stephan 2014-10-22 20:59:40 +00:00
  • 02a7bb488a memport: remove old parameter stephan 2014-10-22 20:49:11 +00:00
  • a3040ddcf3 heteptdig em/v05: merge more IO timing adjustments back into the trunc. stephan 2014-10-22 19:45:53 +00:00
  • 546f7607f2 hetept: timing diagram: add Tx astream stephan 2014-10-22 19:31:20 +00:00
  • d02301f4ac HETEPTDIG EM/V05: Aldec bitfile created (new constraints) kruse 2014-10-22 17:01:06 +00:00
  • 55d03f8bd8 heteptdig em/v05: Add pipeline to ARxM, to help the data signal cross the chip. This pipeline will be merged with srx.deser.sr[]. kruse 2014-10-22 16:59:55 +00:00
  • 40ab29a565 step.l3: Fixed energy bin calculation. terasa 2014-10-22 14:51:17 +00:00
  • 04a7803636 heteptdig em/v05 mem32ee: use posedge xclk for tristate enable stephan 2014-10-22 13:42:47 +00:00
  • b131a0f6b3 stein: added flipflops at the IO-Pads to the IdefX wetzel 2014-10-22 12:47:09 +00:00
  • e27ea925b4 heteptdig em/v05: 32ee memory driver uses xclk to drive D port tristate enables stephan 2014-10-22 12:45:30 +00:00
  • 402c050a51 HETEPTDIG EM/V05: Aldec Adapter bit file updated kruse 2014-10-22 12:25:27 +00:00
  • 78d97c949d heteptdig em/v05: Replicate register tree driving the SRAM D tristate enables The previous code did not replicate the registerd driving the wee, and there is only half a clock cycle from the driving nets to the register. stephan 2014-10-22 12:16:22 +00:00
  • c5b7a56a6f heteptdig em/v05: add SRAM nWE nCE to gtkwave stephan 2014-10-22 12:11:49 +00:00
  • 4a017964bc HETEPTANA EM/V03: Synthesis Resport added kruse 2014-10-22 09:23:30 +00:00
  • 0ba0b3a05a heteptana: v05 gold stephan 2014-10-22 05:58:57 +00:00
  • faaf5deedd heteptdig em/v05: merge -c 3335: memwindow add flag fix stephan 2014-10-21 23:07:15 +00:00
  • e8392c066c tarena: calhist.awk stephan 2014-10-21 22:39:54 +00:00
  • 3ec69551f7 heteptdif em/v05: merged IO timing patches from v05 into trunc stephan 2014-10-21 22:38:22 +00:00
  • 9a10def9fd memport: fix buf in memwindow: heed the _add_ input stephan 2014-10-21 21:49:08 +00:00
  • 20893a6b23 heteptdig em/v05: replicate D output enable registers for timing stephan 2014-10-21 21:15:30 +00:00
  • 1d94327060 heteptdig em/v05: version id gold stephan 2014-10-21 21:14:22 +00:00
  • ed8ba6f0d7 HETEPTDIG EM/V05: Designer project file updated kruse 2014-10-21 16:45:58 +00:00
  • fefecb35ba HETEPTDIG EM/V05: Version number added, bitfile re-created kruse 2014-10-21 16:44:52 +00:00
  • 6baa5d352f heteptdig em/v05: replicate RAM_nCE and RAM_nWE registers stephan 2014-10-21 16:35:08 +00:00
  • 184beee117 heteptdig em/v05: change version number stephan 2014-10-21 15:55:54 +00:00
  • 089f63c6c0 HETEPTANA EM/V03: Bitfile for QM created kruse 2014-10-21 15:47:26 +00:00
  • 00beafd7e4 HETEPTANA EM/V03: Log files for burning added kruse 2014-10-21 15:34:11 +00:00
  • c0b2d22820 HETEPTDIG EM/05: Bitfile for Aldec Adapter created kruse 2014-10-21 15:19:42 +00:00
  • 68f24d87b9 acquire: updated timing to be compatible with Flipflops in IO-Pads; sc: made sure it is compatible wetzel 2014-10-21 13:55:57 +00:00
  • 8c803bee24 hetept timing: move serializer registers into pads stephan 2014-10-21 12:48:44 +00:00
  • 6564657db1 sc_scheduler: fixed a bug wetzel 2014-10-21 11:33:05 +00:00
  • 1d9b35989f sologse: add HIMAC config stephan 2014-10-21 11:16:28 +00:00
  • b758956b75 sologse: add hetept rc stephan 2014-10-21 11:15:07 +00:00
  • 3b1fbc4729 HETEPTANA EM/V03: BGA prototype bitfile created (59 MHz) kruse 2014-10-21 11:14:30 +00:00
  • d2384ab837 HETEPTANA EM/V03: 53Mhz - RTAX2000S (r7_s1.adb) kruse 2014-10-21 10:47:40 +00:00
  • 482cf2426c hetept: add more annotation to the IO timing diagram stephan 2014-10-21 07:13:18 +00:00
  • a18bcc02b6 heteptana em/v03: Add register ATxDD before the inverter feeding srx. The optimizer refuses to invert srx.deser.sr[0] to fit it into the IO pad. So we offer this register for the IO pad. stephan 2014-10-21 06:41:50 +00:00
  • 1e981977b1 package maker: added a comment wetzel 2014-10-20 14:51:10 +00:00
  • 9379fb46de package maker: implemented channel nr mapping wetzel 2014-10-20 14:12:45 +00:00
  • 86041421b6 stein sc scheduler: changed internal control signals to improve stability reliability of the module wetzel 2014-10-20 13:29:52 +00:00
  • aaabd93a9d tarena idata: varius plot anf fit scripts stephan 2014-10-20 08:20:43 +00:00
  • 07ac58b101 adc128s102: merge -c 3311 from ana/em/v03 stephan 2014-10-18 20:59:40 +00:00
  • dba87137e4 adc128s102: add pessimistic delays to the ADC model stephan 2014-10-18 20:58:11 +00:00
  • 2d206bb172 heteptana: add dout[] dump for 100 µs to test log stephan 2014-10-18 20:57:24 +00:00
  • 906bd9c722 hetept: add ADC timing to dig-ana-serial-link drawing stephan 2014-10-18 14:40:07 +00:00
  • 260be6d56e hetept: add ADCs to dig-ana-serial-link drawing stephan 2014-10-18 12:17:58 +00:00
  • 18a0b60072 hetept: add ADCs to dig-ana-serial-link drawing stephan 2014-10-18 12:17:20 +00:00
  • 755560dde6 hetept: dig-ana-serial-link drawing stephan 2014-10-17 22:47:51 +00:00
  • 3a23f654d1 merge -c 3298 from ana/em/v03: pragma synthesis, syn_preserve stephan 2014-10-17 18:26:40 +00:00
  • 8beca7e1bb heteptana em/v03: merge -c 3299-3303 registered inverted ADC control outputs stephan 2014-10-17 17:58:45 +00:00
  • e1dc995b49 adc128s102: add pragma synthesis, syn_preserve to inverted output stephan 2014-10-17 17:37:57 +00:00
  • 7a5126185f adc128s102: merge -c 3298 from ana/em/v03: pragma synthesis, syn_preserve stephan 2014-10-17 17:35:01 +00:00
  • 890d4e88d0 heteptana: use the registered inverted ADC control outputs from aschedule stephan 2014-10-17 17:31:47 +00:00
  • 6382c652ec sfilter: forward inverted adc control outputs stephan 2014-10-17 17:30:40 +00:00
  • d87dba3619 adc128s102: add inverted adc control outputs to aschedule stephan 2014-10-17 17:21:30 +00:00
  • b148e76803 heteptana em/v03: add pragma syn_preserve to ADC control output registers stephan 2014-10-17 09:54:30 +00:00
  • 8adb40c9b3 heteptana em/v03: merge -c 2388,3296: sync with dig/v05 stephan 2014-10-16 21:56:04 +00:00
  • 13a90fb836 heteptdig em/v05: merge r2413-2927: sersplit fixes, irrelevant for synthesis stephan 2014-10-16 21:49:48 +00:00
  • e70cc07b7f heteptana em/v03: update ram sim model from dig/v05 stephan 2014-10-16 21:39:43 +00:00
  • 1b5bf503d8 heteptana em/v03: update ram sim model from dig/v05 stephan 2014-10-16 21:36:40 +00:00
  • b059af4743 heteptana em/v03: gold lost+found stephan 2014-10-16 21:31:59 +00:00
  • 500312eba9 heteptdig sim: 5 reg readout gold stephan 2014-10-16 21:09:24 +00:00
  • 81f46ac1b2 heteptana em/v03: merge -c 3285,3286,3287,3288 stephan 2014-10-16 19:47:21 +00:00
  • b0936c6deb heteptdig: merge -c 2703 from em/v04 stephan 2014-10-16 19:02:35 +00:00
  • d93a1a9f17 heteptdig em/v05: merge -c 3187,3252,3136: minor adjustments stephan 2014-10-16 18:52:16 +00:00
  • 775b0e03b1 heteptana: use the FO parameter to the adc scheduler to replicate the adc control signals to three sets of science ADC pads, and two sets of HK adc pads. stephan 2014-10-16 16:47:41 +00:00
  • 753923daef adc128 filter: support new FO parameter of the adcschedule module stephan 2014-10-16 16:43:33 +00:00
  • 8af5003d17 hkadc: support new FO parameter of the adcschedule module stephan 2014-10-16 16:40:50 +00:00
  • ed6a5555a6 adcschedule: add parameter FO=1 for ADC control signal register replication to fanout to multiple IO pads with minimum delay. stephan 2014-10-16 16:39:43 +00:00
  • f2b2249296 stein: review sc scheduler: spelling, DOUT mux fix, active stephan 2014-10-16 14:04:27 +00:00
  • 917d90eee0 sc sched: redesign of sc sched Finished and tested wetzel 2014-10-16 12:45:09 +00:00
  • b4034866b6 step*.l3: Histogram code for single hit triggers. terasa 2014-10-16 12:22:29 +00:00
  • 770459d9eb sc sched: redesign of sc sched, STILL IN PROGRESS - NOT(!) Finished wetzel 2014-10-15 21:19:41 +00:00
  • 70a0c2b5af stein_ix_controller: changed order of declaration (actel compiler) wetzel 2014-10-15 12:42:45 +00:00
  • f349e044d7 stein_ix_acquire_switch: changed order of declaration (actel compiler) wetzel 2014-10-15 12:41:55 +00:00
  • c7e25fae13 stein_core: changed order of declaration (actel compiler) wetzel 2014-10-15 12:41:04 +00:00
  • 3bc6672b64 stein_adc_controller: changed order of declaration (actel compiler) wetzel 2014-10-15 12:39:47 +00:00
  • 863f0f04b7 Fixed IO bug that appeared during modularization. rasch 2014-10-15 10:46:55 +00:00
  • 4ca4020e35 heteptdig em/v05: merge -c 3180,3188: arb without telemetry stephan 2014-10-15 09:21:48 +00:00
  • 9a71d063d7 heteptdig em v05: new gold use heteptana em/v03 (from v01) not changes to heteptdig synth stephan 2014-10-15 09:17:32 +00:00
  • 2c7808ea68 heteptdig em v05: rep copy from .../v04 stephan 2014-10-15 06:58:15 +00:00
  • 6b55c7d3e5 heteptana em v03: merge -c3269: HSDATA IOpad register stephan 2014-10-15 06:53:50 +00:00
  • 4a615d51d3 heteptana em v03: merge -r2252-3268: hkadc testjig fixes, no synth changes stephan 2014-10-15 06:51:59 +00:00
  • 7d2cb90982 heteptana gold for -c 3264,3269 stephan 2014-10-15 06:46:14 +00:00
  • 6c3616c6df hkadc: Add a register to HSDATA, to allow placement in an IO-pad. This improves round trip delay clk->HSCLK->HSDATA->clk. stephan 2014-10-14 20:42:47 +00:00
  • 30af9f3aa4 hkadc: testjig: reduce number of ADC from 5 to 4 stephan 2014-10-14 20:40:11 +00:00
  • 22b5c9af42 hkadc: make testjig more reproducable, by removing randomness stephan 2014-10-14 20:26:42 +00:00
  • e40c0f79fc hkadc: fix testjig stephan 2014-10-14 20:16:03 +00:00
  • 8a7802a1b5 heteptana em v03: merge -c 3264: SDATA IO pad registers stephan 2014-10-14 18:43:19 +00:00
  • 63e4ec9c56 sfilter.v: This patch adds a register at the DOUT/SDATA input, before it is distributed to four SRAM blocks. stephan 2014-10-14 18:40:42 +00:00
  • 271fd18200 step*.l3: Initial commit of STEP L3 trigger code. terasa 2014-10-14 15:50:13 +00:00
  • cc8db1362d heteptana em: branch v03 from v02 will become QM reason for the change: add IO-register to ASDATA stephan 2014-10-14 14:46:14 +00:00
  • bc941d2433 adamhist.awk now allows to cut on multiplicities stephan 2014-10-14 14:42:07 +00:00
  • c2f526aea1 tarena: new data with filter=2 stephan 2014-10-14 14:41:13 +00:00
  • e6481a358c print.gpt no does enhanced stephan 2014-10-14 14:40:24 +00:00
  • 5b3337e12b tarena: read_delay parameter means (n+1) µs now stephan 2014-10-14 14:39:25 +00:00
  • 32b31790ee pipe: fix indentation stephan 2014-10-14 14:38:38 +00:00