Stephan/solo_altera
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  • 2850fb335a cospi: copy to pub/footprints stephan 2014-01-08 21:37:46 +00:00
  • db1582dcb8 cospi: merge r2448 stephan 2014-01-08 21:32:55 +00:00
  • 40905d6f15 cospi: copy to pub stephan 2014-01-08 21:30:52 +00:00
  • a6401f090f cospi: add logo image stephan 2014-01-08 21:30:34 +00:00
  • 28260c9d9f cospi: copy to pub stephan 2014-01-08 21:29:17 +00:00
  • e49ce8cdcd cospi: remove absolute logo image path stephan 2014-01-08 21:27:24 +00:00
  • faef930066 rpirena: create pub/ stephan 2014-01-08 21:22:35 +00:00
  • b5c89f39ac stein altera: EM smoke test stephan 2014-01-08 21:13:22 +00:00
  • 26031b1a81 hetpreamps: checkout V02 stephan 2014-01-08 21:12:32 +00:00
  • e276b11abe stein: recompile STEIN24.RBF stephan 2014-01-08 21:11:09 +00:00
  • fea8b607d7 removed slow control from 48MHz Domain wetzel 2014-01-07 19:29:45 +00:00
  • dde26a8d0b renamed stein_backend.v to stein_core.v wetzel 2014-01-07 18:41:04 +00:00
  • b5fd3f508d hardwired -sync- wetzel 2014-01-07 18:35:37 +00:00
  • 6de2339cca redesigned classifier wetzel 2014-01-07 18:34:53 +00:00
  • 980692c5a1 added rule for l2trig wetzel 2014-01-07 18:33:59 +00:00
  • 416e590925 updated l2trig.v to stein_l2trig.v filename wetzel 2014-01-07 17:37:45 +00:00
  • 40c2fe7265 moved l2trig.v to stein dir wetzel 2014-01-07 17:35:36 +00:00
  • 9c5270bc9c cospi: fix text, add RPi logo stephan 2014-01-07 16:04:43 +00:00
  • 19d5d437ba cospi: add harness schematics stephan 2014-01-07 15:53:55 +00:00
  • 184b7d42b9 idef-x: unused pixel wirebonds fix, bond to guard stephan 2014-01-06 17:08:56 +00:00
  • e48bfb3d30 idef-x: checkout carrier v04 w/o Invar stephan 2014-01-06 17:02:48 +00:00
  • fd246da4d9 idef-x: add venting hole vias below ASIC stephan 2014-01-06 12:28:02 +00:00
  • b5d90c0669 idef-x: branch v03 to v04 gerber checkout stephan 2014-01-06 12:15:33 +00:00
  • 09e3d3f8e6 added .sch for ENC28J60 christiansen 2014-01-02 15:18:35 +00:00
  • da72bf9f29 cdshield: SSEL and SCLK were swapped stephan 2014-01-02 14:36:25 +00:00
  • 8db5c5127d arm: sdshield: configurable Ssel stephan 2014-01-02 13:46:29 +00:00
  • e099caf501 ethshield: first netlist, magjack stephan 2014-01-02 11:53:47 +00:00
  • cd1103cc26 ethshield: new pcb project stephan 2014-01-02 11:45:38 +00:00
  • 402faf55af HETEPTANA em/v01: added silicon sculptor logfile, amended bitfile/bitfileSummary kruse 2013-12-20 15:47:55 +00:00
  • 849f8a956d HETEPTANA em/v01: Added bitfile/heteptana_RTAXProto.afm, added reports and designer project file kruse 2013-12-20 13:13:31 +00:00
  • dd490dbdc8 HETEPTANA em/v01: deleted netlist, amended synthesis project file kruse 2013-12-20 10:42:33 +00:00
  • 561aec40ac HETEPTANA em/v01: add sdc file for clock, named buffer macros and clock macros kruse 2013-12-20 10:11:42 +00:00
  • 7c4dc14281 hetpreamps: add venting hole stephan 2013-12-20 09:47:53 +00:00
  • 5263ef2678 heteptana em/v01: add truncdiff target to Makefile stephan 2013-12-20 07:21:32 +00:00
  • a3b4589ba1 icucore python: do not start_ after load_hetept stephan 2013-12-20 07:06:05 +00:00
  • 79908c30e6 icucore python: decode 3-bit mosulus_init stephan 2013-12-20 07:05:15 +00:00
  • 9f9cbcacca icucore: image with working astream demux stephan 2013-12-20 07:04:27 +00:00
  • 0288aea51f serializer demux: do not use 5-bit counter @ 384 MHz stephan 2013-12-20 07:03:24 +00:00
  • a71684d216 heteptdig datasheet: states=id,version stephan 2013-12-20 07:01:44 +00:00
  • b7fd35fda4 icucore: pll384, 4x oversampling analog streaming stephan 2013-12-18 11:13:18 +00:00
  • 0d132b4b97 serializer split: 4x oversampling stephan 2013-12-18 10:15:38 +00:00
  • 289256cea9 altera: PLL base clock recovery failed, use 4x oversampling at 384 MHz stephan 2013-12-17 12:02:32 +00:00
  • d0f15c605f sirena avr: read command returns 0xff :-( stephan 2013-12-16 15:38:42 +00:00
  • fa5d2681c2 HETEPTDIG em/v02: Deleted unneccessary folders and files copied from v01, created new programming file kruse 2013-12-16 11:43:35 +00:00
  • 9e8785f6ec heteptdig em/v02: merge -c2408 stephan 2013-12-16 07:46:59 +00:00
  • 9d2ac45fc1 heteptdig: Tx[1] is redundant in sim as well stephan 2013-12-16 07:45:03 +00:00
  • b6cd5b5818 irena: implement option to use the new trigger stephan 2013-12-15 22:07:32 +00:00
  • 0cca8bfef3 heteptdig em/v02: merge 2403,2405: version/Id, move AStream to Tx[1] stephan 2013-12-14 10:22:49 +00:00
  • 3070323214 heteptdig: Tx[1] is the redundant port stephan 2013-12-14 10:18:56 +00:00
  • d8853b974d steincore: update for backend development stephan 2013-12-13 20:46:20 +00:00
  • cdc1fbbfd2 heteptcore: FPGA-Id 0xf2 stephan 2013-12-13 20:45:39 +00:00
  • bf7e38d686 STEP: msg address for HK readout stephan 2013-12-13 19:38:40 +00:00
  • 499752eacf lvds: spice model with broken wire stephan 2013-12-13 18:29:52 +00:00
  • c4dbc7fb3d sirena display: compile fixes stephan 2013-12-13 14:08:45 +00:00
  • 3403899619 sirena display: uart debugger karnjit 2013-12-13 13:43:14 +00:00
  • 5651e5a7a4 PPS schedule: EPD HK only schedule stephan 2013-12-12 20:31:53 +00:00
  • d60f090b56 heteptana: change version text stephan 2013-12-10 20:43:43 +00:00
  • 134d12e825 hetpreamps: new capacitor footprints, add diodes, remove LT LDOs stephan 2013-12-10 17:39:32 +00:00
  • e8de3ec17a eptpreamps: refdes positions stephan 2013-12-10 17:38:00 +00:00
  • 19f69927f6 eptpreamps: add +6V HK channel bias parts stephan 2013-12-10 16:37:26 +00:00
  • 79d6589ba0 HETEPTDIG em/v02: New SDC file (false pathes still missing) prj-files updated edn-files updated and converted for aldec kruse 2013-12-09 16:20:45 +00:00
  • eb1e2f4a24 backend: fixes, including Actel synth merge stephan 2013-12-09 14:57:08 +00:00
  • 587db6d1c8 heteptdig em/v02: new gold stephan 2013-12-09 14:54:41 +00:00
  • 39da87ac81 Changed some blocking assignments to non-blocking assignments kruse 2013-12-09 12:51:39 +00:00
  • 73b213ff11 heteptdig em/v02: update libero prj files stephan 2013-12-09 11:53:45 +00:00
  • dbd3f78877 heteptdig em/v02: merge c2235, 2319-2320, 2323 Calibration mode streaming at 48Mbps through red. Tx stephan 2013-12-09 11:41:15 +00:00
  • fdee9b5a3c heteptdig em/v02: merge c2366,2368,2273 uart and message changes stephan 2013-12-09 08:57:46 +00:00
  • 69d87d3413 heteptdig em/v02: merge r2341:2349 3-bit modulus init 8-bit data header four data formats stephan 2013-12-09 08:54:01 +00:00
  • f0ce97e63a heteptdig em/v02: merge c2277 arb race fix stephan 2013-12-09 08:19:56 +00:00
  • 6de07e7d5b heteptdig em/v02: merge c2279 rb_wait stephan 2013-12-09 08:18:03 +00:00
  • d2db85f9d4 heteptdig em/v02: merge counter fixes stephan 2013-12-09 08:12:11 +00:00
  • 82a25444d5 heteptdig: merge -c2217 from em/v01 stephan 2013-12-09 08:01:06 +00:00
  • b77ef9688a heteptdig em: add log2by8.v stephan 2013-12-09 07:32:50 +00:00
  • 2af1316044 heteptdig em: create branch v02 from v01 stephan 2013-12-09 07:29:54 +00:00
  • e38e61f1ab rpirena: awk helper stephan 2013-12-04 22:02:58 +00:00
  • 3aa658a9ad rpirena: red LED: Ch2&Ch3 coincidence, atomic update of hist file stephan 2013-12-04 21:45:36 +00:00
  • c732cf916f add 2D plot Ch2 vs Ch3 stephan 2013-12-04 21:44:34 +00:00
  • 4e883d83d1 removed unneccessary wa respectively re wetzel 2013-12-04 19:37:43 +00:00
  • 0f79ce4c67 ... wetzel 2013-12-04 19:36:49 +00:00
  • 60e98ad429 extended and improved test jig wetzel 2013-12-04 19:36:30 +00:00
  • 54b556c9b5 fixed a bug wetzel 2013-12-04 19:35:27 +00:00
  • ae4dfd2cf2 hetept doc: Monitoring Parameters stephan 2013-12-04 00:21:56 +00:00
  • 81dcfb4eed backend: three more fe_cntr ports stephan 2013-12-04 00:20:18 +00:00
  • 7d8c638597 sirena: add trigger_class register stephan 2013-12-04 00:19:26 +00:00
  • 3c4eaffc3e backend counters: fix a race stephan 2013-12-04 00:14:05 +00:00
  • a9bf58d928 uart: change nominal bit rate to 114942 baud stephan 2013-12-03 21:24:39 +00:00
  • d681d7c0d7 baud.py: fix rounding, ICU base clock parameter stephan 2013-12-03 19:45:23 +00:00
  • b5370cf4cc message: fix timeout at 24 MHz stephan 2013-12-03 19:38:16 +00:00
  • c48fa9d140 backend: three more fe_cntr replace duplicate t_init by (t_init & ~t_ready) stephan 2013-12-03 19:37:44 +00:00
  • d43d0292a4 ift_parser: add pha parser stephan 2013-12-03 19:33:24 +00:00
  • bbe7e68521 bit rate calculation tool stephan 2013-12-03 12:44:39 +00:00
  • 69d5cd1bb9 fixed a timing bug wetzel 2013-12-03 09:12:11 +00:00
  • a69beab420 burst mode: spelling fixes stephan 2013-12-02 14:00:17 +00:00
  • b2767d63e7 burst mode document stephan 2013-12-02 12:51:22 +00:00
  • d57d84a26a updating integration wetzel 2013-12-02 09:06:44 +00:00
  • f7393e8a62 ... wetzel 2013-11-29 13:38:07 +00:00
  • 480ac6c8cd integration of sc and temp in progress wetzel 2013-11-28 16:14:18 +00:00
  • 815f869c8c sc finished, integration follow today wetzel 2013-11-27 09:04:24 +00:00
  • 8277cf6dc2 still working on slow control wetzel 2013-11-26 09:27:14 +00:00
  • cdfab44451 sirena: add uncompressed data set to nominal science, to compare stephan 2013-11-23 10:52:44 +00:00