Stephan/solo_altera
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  • e397b63995 xrena frontend: add optional ssel input to spi_slave for RPiRENA stephan 2013-10-27 09:42:49 +00:00
  • bb28b390b6 erena sim: fix 12 MHz clock stephan 2013-10-27 09:41:00 +00:00
  • 5e748b9f62 hkadc: pass CLKDIV parameter to aschedule, to allow for 96MHz op in RPiRENA stephan 2013-10-27 09:40:08 +00:00
  • 0d9546f84b rpirena host: HK stephan 2013-10-27 09:35:05 +00:00
  • 707704643d hetept doc: fix apid for memory readout stephan 2013-10-26 14:35:17 +00:00
  • ac45f61c42 hetept: more sirena GSE scripts stephan 2013-10-26 14:34:09 +00:00
  • 313210445d hetept: more analysis scripts stephan 2013-10-26 14:32:17 +00:00
  • 63a28ccb78 hetept doc: minor formatting stephan 2013-10-26 14:30:03 +00:00
  • 9b420fbc4a shaper2u2: streaming mode PPS schedule stephan 2013-10-26 14:28:45 +00:00
  • 77afb57b07 hetept: HK.gpt stephan 2013-10-21 20:57:31 +00:00
  • e8f83a8f8b hetept: initial stream data analysis scripts stephan 2013-10-21 19:44:46 +00:00
  • 8cfdd41d8d eptpreamps: rename center segments to match AC names stephan 2013-10-21 13:08:54 +00:00
  • 578d6be755 rpirena: Altera pinout stephan 2013-10-20 19:37:33 +00:00
  • 5eeeb92344 rpirena: host code, spidev, gpio for Altera config stephan 2013-10-20 19:35:45 +00:00
  • 783a487b45 ccdata: add writeimage to ccdstream.py stephan 2013-10-20 19:33:14 +00:00
  • edbadf30a8 cecederena: comment spelling stephan 2013-10-20 19:30:55 +00:00
  • d8f8bbcb51 Added LCD driver for ATMega32 kruse 2013-10-17 14:43:30 +00:00
  • 8c24c80db1 serializer: clock recovery PLL stephan 2013-10-15 16:49:09 +00:00
  • 0ef749c9ad serializer: Implement a clock merged mode for 48Mbps. The signal provides a rising edge at 24MHz for a pll to lock on. In between the edges are two data bits. The decoder PLL must provide a clock at twice the bit rate, i.e., 96MHz. The encoder needs the bit clock and the data only. stephan 2013-10-15 16:47:49 +00:00
  • 88bee55ee2 sirena: fix syntax fix testjig fix Altera synthesis needs debugging, test sequence development stephan 2013-10-14 21:20:38 +00:00
  • 78ca4c8fbe backend doc: add HET/EPT: frontend streaming mode it stephan 2013-10-14 18:36:17 +00:00
  • 38a7925a69 sirena: copy heteptcore to sirenacore remove analog board ifc instantiate in sirena add evgen stephan 2013-10-14 18:35:11 +00:00
  • c1863c82ee memport: readapt memasync8 from memasync8m stephan 2013-10-14 18:33:02 +00:00
  • 5b0541f7be hetept/doc: add document ID stephan 2013-10-14 18:32:02 +00:00
  • 24356e8bba sirena: evgen_hetept complete and functional stephan 2013-10-13 22:54:43 +00:00
  • 463a2d4471 idefx simulation model now has analogue output for temperature output wetzel 2013-10-10 12:35:53 +00:00
  • 78896066ef hetept: evgen.v started stephan 2013-10-09 21:08:32 +00:00
  • b3932b7f9e idefx simulation model now has analogue output for event read wetzel 2013-10-09 14:17:32 +00:00
  • aab953fe20 idef-x: iarena successfully talking to Idef-X stephan 2013-10-08 13:34:09 +00:00
  • 5ca59f5ebc iarena: fix breakage from last commit stephan 2013-10-08 12:02:21 +00:00
  • 7843acbc11 iarena: fix testpulser address decoder, syntax cleanup stephan 2013-10-08 07:40:16 +00:00
  • d4aeac3fb5 HETEPTDIG - v01: bitfileSummary amended, old bitfile removed kruse 2013-10-07 13:34:05 +00:00
  • f73bbf6e28 HETEPTDIG - v01: New bitfile created kruse 2013-10-07 13:32:41 +00:00
  • ffa1765869 heteptdig em v01: merge r2219: SRAM pin assignments stephan 2013-10-07 12:48:54 +00:00
  • ffc8af3bc2 heteptdig: fix SRAM/EEPROM address and data pin assignments for MEM16EE according to Alexander's table. The previous assignment was made using the flight SRAM datasheet pin names on the adapter, which are irrelevant, since the board level net names are not mapped to the datasheet pin names for the SRAM. Only for the EEPROM the board level names agree with the part names, to facilitate the issue of the magic write sequence. stephan 2013-10-07 12:21:38 +00:00
  • fa84d2de4b heteptdi - v01: Bitfile heteptdig_uart_fast.pdb revised kruse 2013-10-02 09:08:11 +00:00
  • 48d3cb48b2 heteptdig em v01: invert LVDS output polarity stephan 2013-10-02 06:50:23 +00:00
  • 549347eedd ccdrena: gtk poll in follow mode stephan 2013-10-01 19:32:48 +00:00
  • 0bf928a2cd heteptdig v01: bitfiles for fast and slow uart added, bitfileSummary added kruse 2013-10-01 10:43:11 +00:00
  • 654c5ffc16 ccdrena: temporary fix for aborting -F mode stephan 2013-10-01 08:52:37 +00:00
  • 689e3e7f03 heteptdig em v01: merge r 2211-2212: fix MEM16EE stephan 2013-10-01 07:36:38 +00:00
  • 8fe07e2dca heteptdig: fix conenctions to MEM16EE stephan 2013-10-01 07:28:20 +00:00
  • 109ae76c7c memport mem15ee: fix D tristate enable stephan 2013-10-01 07:24:17 +00:00
  • 60cd4e2edd ccdrena: make projections work stephan 2013-09-30 18:17:55 +00:00
  • f0aea0f1eb heteptdig: sim with M16EE stephan 2013-09-30 14:38:43 +00:00
  • 40f798107b heteptdig em v01: merge -r 2206..2207: MEM16EE data pins stephan 2013-09-30 14:02:36 +00:00
  • c3428667a2 heteptdig: fix SRAM data pins, connect DEBUG to unused D pins stephan 2013-09-30 13:59:23 +00:00
  • 0a6d2ceeef heteptcore: provide DEBUG pins stephan 2013-09-30 13:56:54 +00:00
  • ad95a448aa heteptdig em v01: merge -r2204: fix syntax errors for case MEM16EE stephan 2013-09-30 12:54:41 +00:00
  • bcc855d671 heteptdig: fix syntax errors for case MEM16EE stephan 2013-09-30 12:52:54 +00:00
  • dc222dce90 heteptdig em v01: merge r2202: 8-bit DPS header support stephan 2013-09-30 10:32:11 +00:00
  • ce24505325 backend: add 8-bit header mode to data product packets stephan 2013-09-30 10:01:44 +00:00
  • 4085e0a026 heteptdig: raise SEU rate to 100 stephan 2013-09-30 10:00:55 +00:00
  • 66ad9ffb42 heteptdig: raise SEU rate to 100 stephan 2013-09-30 10:00:37 +00:00
  • 3ed86aae5b sirena: icucore: polarity adjustment support for LVDS links stephan 2013-09-30 07:04:21 +00:00
  • 3f80e1ac95 ccdrena: projection: drop diagonals, fix add bug stephan 2013-09-30 06:31:24 +00:00
  • e363b8049d ccdrena: use fifo_halffull for image dump throttle, to avoid loss stephan 2013-09-30 06:28:43 +00:00
  • 3ddfbb6fb4 ccdrena: half size window, partial image continuation stephan 2013-09-30 00:15:45 +00:00
  • 4f11983c56 HETEPTANA - v01 - bitfileSummary amended kruse 2013-09-29 14:35:38 +00:00
  • f1255ccb2a HETEPT - v01 - Libero Project Files added, bitfile and bitfile-summary added kruse 2013-09-29 14:34:51 +00:00
  • 645205c10a ccdrena.rbf: use fifo_halffull for image frames stephan 2013-09-29 11:05:56 +00:00
  • 87d6896cbc ccdrena: allow 2048 column projection, add -F FAST flag stephan 2013-09-29 11:05:11 +00:00
  • 761ecc2712 ccdrena: fix fifo resets, proj mode stephan 2013-09-29 11:03:55 +00:00
  • 0bfd854be6 ccdrena: enable adiff mode in isetup stephan 2013-09-29 11:03:24 +00:00
  • bade085e54 ccdrena: properly format ssize_t stephan 2013-09-29 10:07:13 +00:00
  • 9851a7cd3f ccdrena: properly format ssize_t stephan 2013-09-29 10:06:00 +00:00
  • 0cfd2079db ccdrena: allow 2048 columns stephan 2013-09-29 09:56:47 +00:00
  • f335e9ac6e ccdrena: add ccdrc.py stephan 2013-09-29 09:23:22 +00:00
  • 6ae3d86ea9 ccdrena: c python module for image stream readout, with pygtk frontend stephan 2013-09-29 09:07:22 +00:00
  • 07ec1ed5d8 ccdrena: debug fproj stephan 2013-09-29 00:07:22 +00:00
  • ea9289456e ccdrena fproj simulation stephan 2013-09-28 21:49:22 +00:00
  • 96e8b0432e ... wetzel 2013-09-26 19:57:16 +00:00
  • 8135042077 updated idefx-sim-model - still under construction wetzel 2013-09-26 13:20:52 +00:00
  • 839699224c added gtkw for idefx simulation model wetzel 2013-09-25 18:30:20 +00:00
  • 8beeceac93 Idefx simulation model can now do sc write and read - still under construction wetzel 2013-09-25 18:29:22 +00:00
  • f959fd8269 added file for simulation model of idef-x - under construction wetzel 2013-09-25 11:39:00 +00:00
  • aa492899ac HETEPTANA, V01 - Bitfile, description and logs added kruse 2013-09-25 09:39:44 +00:00
  • f144d7bb5b ccdrena: implement frame projection mode stephan 2013-09-24 20:04:24 +00:00
  • 724b9adabf iarena FAT: RBF with correct read_delay and iostat addr stephan 2013-09-23 10:32:40 +00:00
  • 01e59705aa frontend updated to new slow control interface wetzel 2013-09-23 07:43:12 +00:00
  • 15b9bc78b7 added .gtkw for stein_frontend wetzel 2013-09-20 12:31:55 +00:00
  • c950b90c8f Redesign of slow control scheduler, changed interface! wetzel 2013-09-20 12:05:11 +00:00
  • 03edce6dda slow control and slow control scheduler - still - under construction wetzel 2013-09-20 11:02:51 +00:00
  • a17e78dd49 fix read_delay address stephan 2013-09-19 13:30:19 +00:00
  • 67e5362e54 uccd.py: fix sensor temperature calibration stephan 2013-09-17 23:06:47 +00:00
  • d1a0ea1500 ccd image: fix normalization stephan 2013-09-17 23:06:17 +00:00
  • 34ad834e0c ccdrena: support for recent development stephan 2013-09-16 21:25:06 +00:00
  • 3db42c51e6 ccdimage: parser scripts stephan 2013-09-16 21:20:23 +00:00
  • 9b901eb9de ccdclocks: Extend HS from 6 bit to 8 bit, to accomodate slow vclocks and vbin. Extend edge_shift to delay vclock edges much longer, with configurabe step size. Add IBIN and OSC modes. stephan 2013-09-16 21:18:16 +00:00
  • 954ca840bd uccd.py: define new slow vclock timing, Tv=4µs, 10 MHz pixel clock Add sensor temperature reading to HK() stephan 2013-09-16 21:13:30 +00:00
  • 6e3e129a4f ccd qdriver: add alternative output preamp schematic ¡ do not use for netlisting, contains both versions ! stephan 2013-09-16 21:10:44 +00:00
  • 28515b05b2 cecederena: define unused states and strobes testjig simulates new slow vclock nominal timing testjig parses ccdimage frames stephan 2013-09-16 21:08:25 +00:00
  • 18db911aa3 ccddriver: prevent fifo write when full fix hvalid_pipe for OSC mode stephan 2013-09-16 21:06:08 +00:00
  • 8d3d3e2ed0 ccdimage: add -p pipecmd stephan 2013-09-16 20:59:38 +00:00
  • c4c249a679 working on some issues, not finished yet wetzel 2013-09-16 09:52:38 +00:00
  • e65d9e95ce cospi: board submitted stephan 2013-09-14 20:56:53 +00:00
  • d6e19d2c1c ccddriver: build logs stephan 2013-09-14 20:48:43 +00:00
  • 6f4aa9dc0d ccddriver: stephan 2013-09-14 20:47:42 +00:00
  • 9a2f00f286 add MACRO SER_FIFO_ALTERA stephan 2013-09-14 20:38:09 +00:00
  • b4f8d4a2aa bom.py: use python3, fix continuation indent stephan 2013-09-13 18:05:49 +00:00