Stephan/solo_altera
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  • b5a7b922e9 stein.v udated to pinout interface wetzel 2013-06-17 12:26:24 +00:00
  • 4e8216fda2 moved existing stein.v to the filename stein.v wetzel 2013-06-17 11:44:12 +00:00
  • 29b9fe2e7d deleted new stein.v, because there was already one wetzel 2013-06-17 11:42:52 +00:00
  • 31ec0b95ab added new stein.v wetzel 2013-06-17 11:36:25 +00:00
  • b47b9cd4f7 moved old stein.v wetzel 2013-06-17 11:35:24 +00:00
  • 1abfa6f931 all shaper parameterized stephan 2013-06-17 10:51:22 +00:00
  • 22c9dea6d1 shaper 20-29 parameterized stephan 2013-06-17 10:37:21 +00:00
  • 4a176adbe7 EPT shaper gain factor 2.5 stephan 2013-06-17 10:04:24 +00:00
  • 78e0dc4e4d add a fifo to the icucore transmitter stephan 2013-06-14 20:34:20 +00:00
  • 68a01eff2f fix port assignements, connect fifo_full stephan 2013-06-14 12:30:53 +00:00
  • 6138b8b3d7 bring code and documentation into better agreement stephan 2013-06-11 09:43:32 +00:00
  • 8dc0ef7df6 icucore altera built, but with bogus connections, not reviewed stephan 2013-06-10 15:35:20 +00:00
  • bca8ec358a pps_gen fixed stephan 2013-06-10 14:22:40 +00:00
  • c24e6b62ca pps_gen for sim added wetzel 2013-06-10 13:45:41 +00:00
  • 8c1b65f003 fix icucore interface, with Px pps signal stephan 2013-06-10 12:23:49 +00:00
  • 63e9ce6e1e added temperatur module, does not work correctly wetzel 2013-06-10 11:10:17 +00:00
  • cdd5de178d updated wetzel 2013-06-10 11:09:42 +00:00
  • 9ab5da84d7 updated - not completly testet wetzel 2013-06-10 11:09:18 +00:00
  • da0f9eae41 multiple EPT gain options stephan 2013-06-09 22:32:14 +00:00
  • 6eb2fb1d03 add summary sheet stephan 2013-06-07 18:49:17 +00:00
  • fb072962e7 move refdes, add missing value attributes, fix Makefile ... stephan 2013-06-07 13:47:43 +00:00
  • 27889eb473 fix some comments stephan 2013-06-05 20:08:02 +00:00
  • d91cf7d150 frontend.v block diagram stephan 2013-06-05 18:43:08 +00:00
  • 4bf60fcaef heteptana-actel complete and DRC clean stephan 2013-06-05 12:38:06 +00:00
  • f99ebca943 icucore.v updated wetzel 2013-06-05 10:32:01 +00:00
  • b6b1790dc5 icucore fixes stephan 2013-06-05 10:22:22 +00:00
  • 4da4865395 icucore.v updated - still under construction wetzel 2013-06-05 08:20:07 +00:00
  • c5960a90a9 icucore.v added wetzel 2013-06-05 07:56:22 +00:00
  • f5d2cbdb7c placed all 0805 blocking caps, now need to fix DRC stephan 2013-06-04 16:03:39 +00:00
  • 1d6348b857 Actel only version, still with 0603 blocking caps stephan 2013-06-03 10:34:36 +00:00
  • 3cdbee6af1 LVPECL series resistors set to 316Ω, to comply with the RTAX data sheet stephan 2013-05-31 22:13:43 +00:00
  • 1cc45ea39a fully parameterized itof and itouf stephan 2013-05-31 15:55:37 +00:00
  • c5e5afb47c fix u25tof13 stephan 2013-05-30 22:32:06 +00:00
  • 110a144936 move itof to separate file, prepare to add more stephan 2013-05-30 20:41:58 +00:00
  • a999643a32 Add modulus limit to data packet generation. Use cases: Data packets then do not contain lowest cadence data. Uncompressed burst mode trigger packets, that may have gaps. stephan 2013-05-29 09:59:46 +00:00
  • 1dc83320c8 frontend block diagram stephan 2013-05-28 21:31:50 +00:00
  • 1e761c6097 LVPECL series resistors set to 316Ω, to comply with the RTAX data sheet stephan 2013-05-28 15:16:56 +00:00
  • 1b71f87128 Pinout of heteptana now with LVPECL kruse 2013-05-28 15:14:14 +00:00
  • abe508a53e Beginning of a dataproduct compiler stephan 2013-05-27 20:32:55 +00:00
  • 5f2c4e02d5 renumber the condition bits 00: unconditional 01: S 10: ~C 11: C opcode zero is now an unconditional STOP stephan 2013-05-27 20:10:21 +00:00
  • a4cec893f6 heteptana.v adjusted for target actel, libero project and constraint files updated kruse 2013-05-27 14:51:17 +00:00
  • 32dbc26d72 moving towards simulation of EPT events stephan 2013-05-27 13:29:22 +00:00
  • 4e76b0ac94 work on HET trigger stephan 2013-05-26 21:12:51 +00:00
  • 8c345a48dc add e_full stephan 2013-05-26 20:45:25 +00:00
  • 77cdc3e84f bfifo use edac72read2, i.e., one more register in the edac pipeline stephan 2013-05-24 16:19:42 +00:00
  • a3520df12c syntax fix stephan 2013-05-24 15:56:23 +00:00
  • f5fd04d9ef HETEPTANA project updated, design runs at 49MHz kruse 2013-05-24 14:22:27 +00:00
  • bc7d5f06a3 fix EC, needs address stephan 2013-05-24 12:51:36 +00:00
  • 2cd598bee5 add EC option, error correction, to sampleram, use for dranbuf stephan 2013-05-24 11:43:51 +00:00
  • de9cf784ca add NO_SAMPLES option stephan 2013-05-24 08:51:45 +00:00
  • 999a90dbac add afull to bfifo, used for serfifo stephan 2013-05-24 06:51:34 +00:00
  • f1d120ac4c sfilter test with tripple redundant ACTEL RAMS and adc128s102 stephan 2013-05-23 21:24:20 +00:00
  • fd97baaeb3 use tripple redundant SRAM stephan 2013-05-23 21:09:15 +00:00
  • 5f5ed1831f unified GENSRAMs stephan 2013-05-23 21:01:25 +00:00
  • e49bc82e18 samplestore output mux module stephan 2013-05-23 20:04:20 +00:00
  • af3361bd25 add one register to the output of the sampleram stephan 2013-05-23 19:59:37 +00:00
  • 20634ddcf4 parameterized output delay in fschedule stephan 2013-05-23 18:58:40 +00:00
  • 930ea9ecf1 comments stephan 2013-05-23 17:29:52 +00:00
  • aaa44b84e1 do not check in .log fles, use .gold stephan 2013-05-23 17:24:39 +00:00
  • b7b60d7a35 from 4 to 8 FLAGS bits stephan 2013-05-23 17:23:57 +00:00
  • 53feb530b6 from 4 to 8 FLAGS bits stephan 2013-05-23 17:23:16 +00:00
  • 94a17fa5e4 add UART3MHZ stephan 2013-05-23 17:19:19 +00:00
  • 5af150ec52 minor gold diff for linenumber moves stephan 2013-05-23 13:21:20 +00:00
  • 3739232dab replace spififo with EDAC bfifo(16-bit) in secondcyclone slave stephan 2013-05-21 21:23:36 +00:00
  • 49b9fc195a Tutorial for Libero IDE added kruse 2013-05-17 14:53:15 +00:00
  • 704eba7d84 Libero Workspace updated kruse 2013-05-17 13:23:32 +00:00
  • b0352b34bc Libero Workspace cleared of unnecessary files kruse 2013-05-17 12:13:23 +00:00
  • 5bf070a50b gold for real L3 processor stephan 2013-05-17 09:55:19 +00:00
  • 4d27667dce Typo corrected kruse 2013-05-17 08:27:52 +00:00
  • 9400298cf5 sim fix new opcode bits stephan 2013-05-17 06:02:40 +00:00
  • 6d34846751 separate transmitter clock from main clock stephan 2013-05-16 15:25:06 +00:00
  • dab1716072 DIRENA stephan 2013-05-15 20:11:01 +00:00
  • 4edc7e3eba minor fixes stephan 2013-05-14 14:31:02 +00:00
  • a2247e1493 complete stephan 2013-05-13 22:40:03 +00:00
  • 90e206ce6f A good part of the L3 instruction manual stephan 2013-05-13 16:57:56 +00:00
  • acd519b0af updated with new signals from swtich module wetzel 2013-05-13 12:28:52 +00:00
  • 0763c366a1 under construction wetzel 2013-05-13 12:27:57 +00:00
  • 2925723365 updated with new signals wetzel 2013-05-13 11:26:09 +00:00
  • d21f5f4375 still under construction wetzel 2013-05-13 11:25:17 +00:00
  • 021228ab70 updated the aquire include path wetzel 2013-05-13 11:20:57 +00:00
  • 840cc49bdd various l3 assembly targets stephan 2013-05-13 08:10:50 +00:00
  • 9b3a186a12 move ept1_entry after the didHET flag use 0xe2 for Z init, to make the verilog sim happy stephan 2013-05-13 08:09:37 +00:00
  • 94ab54dddd don't change forwardfile if no changes were detected use l3dis() for verbose>=3 stephan 2013-05-13 08:08:23 +00:00
  • b1685bd809 fix default format stephan 2013-05-13 07:47:42 +00:00
  • 9b1b49a3a5 avoid emacs hassles stephan 2013-05-13 07:46:38 +00:00
  • 92627e8ed7 move gtkw out of the lxt dir, remove lxt dir from repro stephan 2013-05-13 06:55:23 +00:00
  • 849f012ed0 support float symbols in l3.py add calibration factors to ept_calib.l3 stephan 2013-05-11 22:48:04 +00:00
  • 4abba6f428 add POKE stephan 2013-05-11 22:14:46 +00:00
  • 7fe922b80e split ept.l3, rework stephan 2013-05-11 20:47:58 +00:00
  • 05a4e5c3b6 use MULI, not SUB for Z init stephan 2013-05-11 20:46:40 +00:00
  • fe35ff7f6d add ept.l3v .include dependencies stephan 2013-05-11 20:45:53 +00:00
  • a972425e13 opcode[3] assigned for Rx/Ry codes NOP added stephan 2013-05-11 20:44:12 +00:00
  • cdbd38deb0 make negative shift more robust stephan 2013-05-11 20:42:06 +00:00
  • 94eb285d1a properly treat negative input stephan 2013-05-11 20:34:23 +00:00
  • a213da272a l3 disassembler ans simulator stephan 2013-05-11 20:30:16 +00:00
  • 2e48f53954 change trim semantics trim=max(min(opA,obB),opB+opC)-opB stephan 2013-05-11 10:45:36 +00:00
  • f235a429fc fix sign extension for right shifts stephan 2013-05-11 10:44:12 +00:00
  • 6f3723a069 .print stephan 2013-05-11 10:43:11 +00:00
  • 1a1ef95377 eptpreamps submission stephan 2013-05-11 10:40:15 +00:00
  • 4875e4f099 swap TX - Rx port names stephan 2013-05-11 10:39:16 +00:00