Stephan/solo_altera
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  • 8f6ec71547 erena oscilloscope stephan 2012-08-15 00:07:01 +00:00
  • 8babfc05d7 Lauris D-50 pinout, ADC and MUX mapping stephan 2012-08-14 16:03:46 +00:00
  • 15cbb9e957 heteptana HK readout stephan 2012-08-14 06:52:49 +00:00
  • 4d95cd2e44 resp timeout stephan 2012-08-14 06:52:18 +00:00
  • 346a3e9e4d try to avoid verilog syntax in C programs stephan 2012-08-10 08:02:46 +00:00
  • 93f405a581 flyrena testbench runs three triggers stephan 2012-08-09 21:32:19 +00:00
  • b775095640 add -f follow and -c channels options to difile stephan 2012-08-09 17:29:44 +00:00
  • adb82cb14c preliminary config for et088 stephan 2012-08-09 12:42:27 +00:00
  • b5fec917c7 long ana config messages stephan 2012-08-09 00:41:03 +00:00
  • 7aaf8a9bfd draft trigger module for flight stephan 2012-08-09 00:39:37 +00:00
  • d68200604d add reset to rb_sch and confmem stephan 2012-08-09 00:38:31 +00:00
  • 598d0a8211 flyrena housekeeping works in hardware stephan 2012-08-07 21:38:57 +00:00
  • 3f04a32636 readcmd, strobe defs stephan 2012-08-07 14:47:05 +00:00
  • 5de85f5e9b fifo 2 config, fixes stephan 2012-08-07 14:46:36 +00:00
  • d1cfc8d8ff flyrena register readback infrastructure, untested stephan 2012-08-07 08:49:43 +00:00
  • d5515f46e6 fix flyrena synthesis stephan 2012-08-06 18:21:28 +00:00
  • 5fd50b09e1 buglet stephan 2012-08-06 18:16:49 +00:00
  • 0c24e00282 arm gains flyrena menu stephan 2012-08-06 14:17:53 +00:00
  • 658f5c574a flyrena gains a pps scheduler stephan 2012-08-05 21:58:28 +00:00
  • 499952dac2 flyrena synth for altera fixed stephan 2012-08-05 00:08:16 +00:00
  • 170679dea6 flyrena arb telemetry fixes stephan 2012-08-04 23:52:56 +00:00
  • 5635ae7a70 flyrena message ifc, with arb and t_copy stephan 2012-08-04 22:55:38 +00:00
  • 23d7ee37fb flyrena sim inclusive heteptana stephan 2012-08-04 16:30:28 +00:00
  • 9897c012ed proper adc128s102 model, fix din1 stephan 2012-08-04 16:07:13 +00:00
  • 08716ecb51 paramerize width and frequency stephan 2012-08-04 16:05:17 +00:00
  • 165d9bca9b kludge for fixing corrupted state of spi_fifo at statup stephan 2012-08-04 16:04:16 +00:00
  • 2446fbf978 hkadc clk net fix stephan 2012-08-03 23:52:42 +00:00
  • a1c2bf81d9 hkadc gold file stephan 2012-08-03 23:38:56 +00:00
  • 7562f0e9ea hkadc fix stephan 2012-08-03 23:37:45 +00:00
  • 77b90981c4 48 MHz ser_clk without PLL, hkadc stephan 2012-08-03 23:34:41 +00:00
  • 02a03ad427 run flyrena link at 48 MHz without ser_clk PLLs stephan 2012-08-03 19:16:15 +00:00
  • 64d73758e8 verify that serializer.v works at 48MHz without PLLs stephan 2012-08-03 17:10:30 +00:00
  • 4cf77405bd flyrena support stephan 2012-08-03 14:45:48 +00:00
  • d79094e5ac fix part name, R1 parameter stephan 2012-08-03 14:44:13 +00:00
  • 78496cce9b define values, gains, channels stephan 2012-08-03 14:43:26 +00:00
  • 43ec929a56 fix dranbuf address bus size stephan 2012-08-03 14:29:02 +00:00
  • c6b3bcc910 tell aarena about the packet size, parameter NC stephan 2012-08-03 14:27:40 +00:00
  • 520a7bd25a adctest.py lost+found stephan 2012-08-03 08:32:41 +00:00
  • 7dcb287869 adapt adctest as heteptana stephan 2012-08-02 21:51:29 +00:00
  • 3bdd6f6eb1 fix flyrena pinout stephan 2012-08-02 19:48:55 +00:00
  • 5b969e5b0b fix data plugin connector orientations stephan 2012-08-02 13:45:40 +00:00
  • 978d5a2471 fix power routes broken by vias stephan 2012-08-02 13:23:11 +00:00
  • 2685cef24f fix values, bom stephan 2012-08-02 13:05:32 +00:00
  • 3f19842f4b FLYRENA stephan 2012-08-02 11:10:47 +00:00
  • d411f2aac4 send a message when clock is set stephan 2012-08-02 11:10:03 +00:00
  • ea21716c4b add clean target stephan 2012-08-02 09:58:50 +00:00
  • d4f8e3dea4 fix altera_read_packet stephan 2012-07-31 21:31:59 +00:00
  • 18f8232241 ETH setup, SHORT_PACKETS stephan 2012-07-31 20:52:21 +00:00
  • e70acc7a49 issue a message when somebody connects via UDP stephan 2012-07-31 20:36:42 +00:00
  • 803fef04e1 irena: SHORT_PACKETS synthesis fixes stephan 2012-07-31 13:19:28 +00:00
  • 966683aa80 irena: SHORT_PACKETS stephan 2012-07-31 13:02:39 +00:00
  • 4d4c29df09 Fastpath reduced to one cycle, other fastpath (secondlast cycle) is now taken care of by the l3registerfile-module kruse 2012-07-31 12:27:09 +00:00
  • 7c2d2cd6a6 Temp-files removed kruse 2012-07-30 17:07:13 +00:00
  • 2fda8ceeec Minor source code optimizations kruse 2012-07-30 17:06:06 +00:00
  • f51193be47 Unused files removed kruse 2012-07-30 15:44:46 +00:00
  • 2bfc39acf8 EDAC-memory added to design, vpi-programming working, regmem-width now 29 bits kruse 2012-07-30 15:28:25 +00:00
  • 176294bc65 more pirena analysis scripts stephan 2012-07-29 22:32:07 +00:00
  • 54132e6b2c pirena SN4 analysis code stephan 2012-07-28 09:40:23 +00:00
  • 215b7ffc56 VPI-programmer now synchronous to clk, regmem still not working kruse 2012-07-27 16:39:55 +00:00
  • 8ead12a5e4 fix indents stephan 2012-07-27 15:03:14 +00:00
  • b4792d7938 tell piparser the ADC config stephan 2012-07-27 15:02:52 +00:00
  • 1d2c3c7493 applied diff -c 1185 ../irena.sch to erena.sch stephan 2012-07-27 15:02:19 +00:00
  • 6fe671f7d3 applied diff -c 1185 ../irena.sch to cecederena.sch stephan 2012-07-27 15:00:54 +00:00
  • d13472d35a applied diff -c 1185 ../irena.sch to sirena.sch stephan 2012-07-27 14:59:31 +00:00
  • 619d6d633e applied diff -c 1185 ../irena.sch to arena.sch stephan 2012-07-27 14:49:30 +00:00
  • e0a99de733 applied diff -c 1185 ../irena.sch to pirena.sch stephan 2012-07-27 14:46:25 +00:00
  • 668f5b17a7 fix DAC driver feedback stephan 2012-07-27 13:44:04 +00:00
  • 2453d1ead2 fix l3code wa1 stephan 2012-07-27 12:09:24 +00:00
  • 40e4cb9544 VPI-programming-interface working kruse 2012-07-27 11:43:10 +00:00
  • 60e20fa61c R9/R10 10k->1k, R3/R4 4.7k->1k stephan 2012-07-26 06:57:55 +00:00
  • bc032d9841 some consistency fixes stephan 2012-07-24 20:36:13 +00:00
  • ab2ee90302 vpi-programming-interface enhanced kruse 2012-07-24 15:30:51 +00:00
  • a03db073e1 hvps setup for Semra stephan 2012-07-24 09:24:40 +00:00
  • b0d2e54aaa hvps setup for Semra stephan 2012-07-24 09:23:03 +00:00
  • 21ef1f1da6 EDAC-Memory-banks used in architecture of the l3, NOT working so far kruse 2012-07-23 15:31:48 +00:00
  • 60c6619127 implement constant read latency, ra/re registered at input stephan 2012-07-23 14:19:34 +00:00
  • 1f63495660 fix iw port data bus, rv output stephan 2012-07-23 13:34:51 +00:00
  • 9c24c32285 fix bom for UHF transistors stephan 2012-07-23 12:36:46 +00:00
  • ddcf9b1664 fix swapped UHF transistor types stephan 2012-07-23 12:25:25 +00:00
  • 81a33a6d4c savefile forgotten... kruse 2012-07-22 12:39:24 +00:00
  • 4f99d96241 Stephans RAM-Interface added to rep kruse 2012-07-22 12:28:47 +00:00
  • bd91f8ea80 memport_test, first successfull cycles, with EDAC stephan 2012-07-18 09:36:27 +00:00
  • 607896f037 lost+found stephan 2012-07-18 07:11:04 +00:00
  • 6955fc203c memport_test, first successfull cycles, with EDAC stephan 2012-07-18 07:08:03 +00:00
  • 87348b5289 sirena with SPI master stephan 2012-07-17 16:38:51 +00:00
  • 60ee06f917 tran and ac, both do not work nurani 2012-07-17 09:45:15 +00:00
  • 602a19bf21 l3code simulation success stephan 2012-07-16 23:12:05 +00:00
  • 8dd310c3c7 fix sirena for Altera syntax contraints stephan 2012-07-16 19:58:21 +00:00
  • 4f6dcaf64b add hkspi to sirena stephan 2012-07-16 19:48:42 +00:00
  • 2378e2e70b hk spi interface stephan 2012-07-16 18:35:34 +00:00
  • 482370fe02 EDAC protected config table memory stephan 2012-07-16 14:11:40 +00:00
  • b41aee404b add new "single" layer names stephan 2012-07-16 11:30:11 +00:00
  • 2bc05f5b70 ongoing work on EDAC protected memories stephan 2012-07-16 11:28:59 +00:00
  • 2a183ce5a1 fix a fre net names stephan 2012-07-16 11:25:46 +00:00
  • cc570f6277 flyrena altera skeleton stephan 2012-07-16 11:24:16 +00:00
  • 25ddc776ac add init write port stephan 2012-07-14 09:08:12 +00:00
  • c46112d621 unregistered outputs stephan 2012-07-14 08:27:11 +00:00
  • fd943c11db add rv signal to graphic stephan 2012-07-14 08:16:16 +00:00
  • 31ad3d967a add comments, email to Martin stephan 2012-07-14 08:11:18 +00:00
  • d376d33215 L3 register file with EDAC, fast bypass stephan 2012-07-14 07:34:36 +00:00