Stephan/solo_altera
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Commit graph

  • cc73ed7195 lost+found stephan 2012-07-13 14:27:42 +00:00
  • d21f7202c6 start of a fast hamming protected register file for L3 stephan 2012-07-13 14:27:25 +00:00
  • 1b0893c26b eliminate one hole size: power via from 0.92mm to 35mil stephan 2012-07-13 08:59:43 +00:00
  • ddbad331c2 swap power and signal layers stephan 2012-07-12 23:06:47 +00:00
  • cdea9aa885 add Makefile stephan 2012-07-12 22:55:53 +00:00
  • 49b9ae610e fix digital power return path of the ADC stephan 2012-07-12 22:39:38 +00:00
  • da10f34707 add caps to unused HK channels stephan 2012-07-12 22:02:19 +00:00
  • e8e83e857c add blocking caps to RAM stephan 2012-07-12 21:11:18 +00:00
  • 109ac37b40 flyrena with ground ring on both sides stephan 2012-07-12 16:51:31 +00:00
  • c0615694ea fixes, especially the central poly hole stephan 2012-07-12 14:57:14 +00:00
  • 6f71382f2f add LDVS ref resistor stephan 2012-07-12 10:52:52 +00:00
  • 24991443ca flyrena DRC clean, refdes clean, soldermask clean stephan 2012-07-12 10:50:59 +00:00
  • 49e73a144a flyrena complete stephan 2012-07-12 02:04:40 +00:00
  • d32356bcb6 RAM with address demux stephan 2012-07-12 00:04:15 +00:00
  • 03e8ebff1e RAM with address demux stephan 2012-07-12 00:03:33 +00:00
  • a027886d3a flyrena missing symbols stephan 2012-07-11 20:05:06 +00:00
  • c68e37d262 flyrena almost done stephan 2012-07-11 20:01:21 +00:00
  • 52e8db6585 fix pinseq for spice stephan 2012-07-11 19:59:06 +00:00
  • df3dba3052 more spice models stephan 2012-07-06 10:00:36 +00:00
  • 81e2406731 image for tests with Javi stephan 2012-07-05 16:29:58 +00:00
  • 770a76d79a new altera images stephan 2012-07-05 16:29:03 +00:00
  • 83375048ef read_counters, findsirena stephan 2012-07-05 16:27:54 +00:00
  • 9104f34d0f lasc module stephan 2012-07-05 16:26:37 +00:00
  • a2d84ab415 altera_read_packet rewritten stephan 2012-07-05 16:24:55 +00:00
  • d87fbffb09 add BF862 model from http://www.nxp.com/documents/spice_model/BF862.prm stephan 2012-07-05 10:32:11 +00:00
  • f7cf885842 add BF862 model from http://www.nxp.com/documents/spice_model/BF862.prm stephan 2012-07-05 10:31:18 +00:00
  • f827762d51 preamp spice simulation stephan 2012-07-05 10:17:35 +00:00
  • 7e02e7ae9d voltage regulator work stephan 2012-07-04 17:25:00 +00:00
  • 71d32e413a fix syndrom36 stephan 2012-07-02 16:41:25 +00:00
  • b352264a31 add syndrom36, untested stephan 2012-07-02 12:43:26 +00:00
  • f56371a885 First step toward EDAC-controlled memory, not tested kruse 2012-06-23 22:37:29 +00:00
  • fb6f3b575a Variable rename before major pipeline rebuild kruse 2012-06-22 12:40:44 +00:00
  • 109e30d4c1 do not assert fifo_full for starimage acquisition stephan 2012-06-19 11:47:12 +00:00
  • 54ba6ea34b fix mem port readback stephan 2012-06-19 11:46:13 +00:00
  • 03bd97df77 merged fixes stephan 2012-06-17 13:16:02 +00:00
  • 73d2224341 comments and fixes for the SRAM interface stephan 2012-06-16 19:24:04 +00:00
  • 7ead6defe9 add ienable()/disable() stephan 2012-06-16 17:17:26 +00:00
  • e99e427c00 ADCid() stephan 2012-06-16 13:43:05 +00:00
  • a0e67d5381 image capture and starfinder bitstreams, default: image stephan 2012-06-16 13:42:26 +00:00
  • 04d9a31110 add ix_read_delay() stephan 2012-06-15 13:00:12 +00:00
  • 8092724b9e add read_delay register at addr IX+7 stephan 2012-06-15 12:53:14 +00:00
  • c6c2a4c4a7 VTEST, VDD0 filter, VBIAS filter added, schematics updated stephan 2012-06-15 09:35:33 +00:00
  • b3c46f4203 about to incorporate Olivier's comments stephan 2012-06-15 06:09:43 +00:00
  • 7851de85dd add delay between TRIG and READ stephan 2012-06-14 13:03:56 +00:00
  • ba4db64eb2 fix soldermasks, add text stephan 2012-06-08 10:00:34 +00:00
  • 959d14fe8f about to review preamp layout for v01 order stephan 2012-06-08 08:38:11 +00:00
  • 52a3e76c09 Missing documentation file added kruse 2012-05-30 14:02:35 +00:00
  • a347c236f7 Design working with ~50MHz kruse 2012-05-30 14:01:55 +00:00
  • 29f815c36a all warnings fixed stephan 2012-05-29 15:50:33 +00:00
  • 1f76b3a3d5 Lauri's ECR controller stephan 2012-05-29 15:21:41 +00:00
  • cc110337c9 VPI compatability introduced, ram-interface now the same as for Libero, documentation started kruse 2012-05-29 12:36:12 +00:00
  • b5899613fc eptpreamps complete, DRC clean stephan 2012-05-22 09:59:46 +00:00
  • 2539313cd6 Two different modules for CMP implemented, conditional execution and rudimentary (and not well tested) JUMPS implemented kruse 2012-05-11 15:30:54 +00:00
  • 66916c81d0 flyrena: moved arena onto soloboard frame stephan 2012-05-09 08:53:32 +00:00
  • 797100fb79 idef-x with baseline sample, scope mode parser stephan 2012-05-07 16:22:52 +00:00
  • 410b70158a iarena synth fixes stephan 2012-05-07 16:03:08 +00:00
  • 7065698483 idef-x: add clock and baseline sample, 40 words packets stephan 2012-05-07 15:54:40 +00:00
  • 2bdb1f1739 LDOs, USB, RS232 added stephan 2012-05-07 14:15:09 +00:00
  • 432dbf6846 LDO symbols: add R1 parameter, STO233 version stephan 2012-05-07 14:14:27 +00:00
  • 0d93c10156 flyrena copied from arena stephan 2012-05-07 06:22:43 +00:00
  • bc61c76b84 uccd: fix for 80MHz stephan 2012-05-01 20:24:25 +00:00
  • e8f8b83eee New Register-Memory-Interface now working kruse 2012-04-30 14:07:49 +00:00
  • e3ca8808e2 parameterized pipeline depth stephan 2012-04-29 23:49:04 +00:00
  • 769461ce29 ccdimage ADC data fixed stephan 2012-04-29 23:48:08 +00:00
  • d300307882 impelement ADC pipeline and faster sampling option stephan 2012-04-28 11:17:45 +00:00
  • 81ced621fb arm: initialize RTC if Y<2000, add time variable stephan 2012-04-27 15:01:23 +00:00
  • b4ddac986f New memory interface to register memory implemented. Fastpath has now two stages, last cycle and secondlast cycle, but is not working yet kruse 2012-04-27 14:19:36 +00:00
  • 62ce9c78c8 eptpreamps ldos added stephan 2012-04-22 20:06:35 +00:00
  • 6166eb4252 refdes stephan 2012-04-22 12:15:14 +00:00
  • cbbfda4ca3 straighten the traces stephan 2012-04-20 19:10:34 +00:00
  • 59c94368b0 2mm milling radius, shall be smaller, if possible stephan 2012-04-19 14:47:04 +00:00
  • 4ec3785fd1 gerber zip and README stephan 2012-04-19 14:16:24 +00:00
  • 85adf7ea1c flex completed stephan 2012-04-18 18:43:54 +00:00
  • 76ad527daa Sascha\'s comments applied stephan 2012-04-18 13:55:16 +00:00
  • 6a56d2e6d5 gerber output stephan 2012-04-18 13:37:18 +00:00
  • df74590cc4 first draft distributed stephan 2012-04-18 09:58:51 +00:00
  • f95a7df8a1 complete ?? stephan 2012-04-18 00:36:57 +00:00
  • a52b3fd9b8 Add 2nd VDDD line stephan 2012-04-17 19:43:47 +00:00
  • c44e659741 first asic bond patterns stephan 2012-04-17 19:15:09 +00:00
  • 6d9ff92e8c fix fat capacitor values, add non-flight opamp footprint stephan 2012-04-17 18:48:37 +00:00
  • 008e8f1e9e Module cmp.v added, all parts of ALU now available and tested, memory access fault corrected kruse 2012-04-17 14:05:31 +00:00
  • 4b9318c98e Modules sub and pha added, hist amended (now works with u5 instead of u8), memory problems partially solved (I'm still not satisfied with the speed), modules tested. Modules CMP1 and CMP2 still missing, module sub not tested kruse 2012-04-16 15:16:31 +00:00
  • 74541fae4b more symbols for hetpreamps stephan 2012-04-15 20:21:36 +00:00
  • 476ff5f604 fix -h stephan 2012-04-15 20:19:24 +00:00
  • 37eb135e01 fully spell nF with an F stephan 2012-04-15 20:09:48 +00:00
  • 08674e6d3c fully spell nF with an F stephan 2012-04-15 20:09:06 +00:00
  • cb5a6922f7 bom values added stephan 2012-04-15 20:02:53 +00:00
  • 1c863754de text, refdes fixes stephan 2012-04-15 19:33:09 +00:00
  • 9d478f5884 fixed LDO prolarity swap, dooh stephan 2012-04-15 17:06:08 +00:00
  • 7954d540d2 keywords prop set stephan 2012-04-15 13:14:39 +00:00
  • fc016de3fc common mode filters added stephan 2012-04-15 13:08:32 +00:00
  • 5b96b8d62e HK stephan 2012-04-15 02:50:30 +00:00
  • 56ac913cce Vfet LDO and output wireing stephan 2012-04-14 23:44:32 +00:00
  • 2f3a00738e two LDOs done, with non-flight option stephan 2012-04-14 16:58:00 +00:00
  • 0ee8f8760c ADD and ADDI tested, seem to work as expected, faulty memory access in cpu.v fixed, works correctly now, but still too slow kruse 2012-04-14 15:27:54 +00:00
  • d07cd591dc preamps with lid ground pad on UBs stephan 2012-04-14 09:20:54 +00:00
  • 3adef50de2 preamps without grounded UB cases stephan 2012-04-13 20:59:00 +00:00
  • ccd3a5260f Modules Adder and Addi amended, still not working properly, Memory Access in cpu.v faulty kruse 2012-04-13 18:52:44 +00:00
  • 0b61dfc88d ept preamp board first picture stephan 2012-04-13 14:21:29 +00:00
  • 0e8dbbcc0f ept preamp board first picture stephan 2012-04-13 14:21:17 +00:00