Stephan/solo_altera
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  • 0122f98bc6 encode done nixdorf 2011-12-21 01:07:19 +00:00
  • 286b3a2b9c i128 now without passthrough logic stephan 2011-12-21 00:09:08 +00:00
  • 2ed3810d03 i128 with infered rams with passthrough stephan 2011-12-20 23:45:41 +00:00
  • a29ef2224d add IPLOT() demanuel 2011-12-19 12:38:41 +00:00
  • c6c5260588 remove buggy settings stephan 2011-12-19 11:42:03 +00:00
  • d7337185cb update FPGA code stephan 2011-12-19 11:31:03 +00:00
  • e4002ce7d4 get the virena going ... stephan 2011-12-19 11:28:04 +00:00
  • 467ee08efd install initail test settings stephan 2011-12-19 11:26:55 +00:00
  • 5a9cfe6cd2 get the virena going ... stephan 2011-12-19 11:26:00 +00:00
  • dcebb81a75 fix l2 channel addresses stephan 2011-12-19 11:25:18 +00:00
  • 5d1cd067b7 varena_parser stephan 2011-12-19 11:23:57 +00:00
  • 437f2382d3 ix_reset to use inject stephan 2011-12-19 11:23:12 +00:00
  • 1716628649 add HK units mV stephan 2011-12-19 11:22:46 +00:00
  • c5d645f903 testpulse to use inject stephan 2011-12-19 11:22:13 +00:00
  • 3b78b46158 fix or operator stephan 2011-12-19 11:21:28 +00:00
  • e06dfda74f fixed broken broken decoding nixdorf 2011-12-15 18:28:47 +00:00
  • fe93688756 added wire for readability nixdorf 2011-12-15 17:50:30 +00:00
  • 5bc92208f4 fix Makefile stephan 2011-12-15 16:55:42 +00:00
  • 435ddc1cff use wire for duplicated expression stephan 2011-12-15 16:55:33 +00:00
  • ef6ad47227 notation changed nixdorf 2011-12-15 00:46:42 +00:00
  • 7a6f94b6e9 fixed ANDing differing bitlength in mask generation nixdorf 2011-12-15 00:42:34 +00:00
  • a43cc86e1d decode rounding corrected nixdorf 2011-12-15 00:35:17 +00:00
  • 0a397e9754 AD7276 option and trigger added stephan 2011-12-15 00:14:11 +00:00
  • ff29b87270 encode.v: added decoding nixdorf 2011-12-14 07:24:01 +00:00
  • 45645656bf encode.v: working but decoding missing nixdorf 2011-12-14 07:14:04 +00:00
  • 735a7ec8af fix for input-msb >7 nixdorf 2011-12-14 05:02:53 +00:00
  • 64c2280c6c minor bugfixes nixdorf 2011-12-14 03:27:31 +00:00
  • d03e6f463a fix rpx without hole stephan 2011-12-13 22:13:52 +00:00
  • 7fe2c6a80e open soldermask on some vias stephan 2011-12-13 19:48:31 +00:00
  • cd4f9118bd starfinder complete, no trigger yet stephan 2011-12-09 10:15:17 +00:00
  • 2bfd4295a5 logic analyser stephan 2011-12-09 09:50:13 +00:00
  • e3757175b8 in scope readout mode, only read nsums samples stephan 2011-12-09 09:49:27 +00:00
  • 6f7c92d221 misc fixes, deadtimes stephan 2011-12-09 09:48:56 +00:00
  • 8bf6de0372 add default config value column stephan 2011-12-09 09:47:48 +00:00
  • 1de83e7bfa ecmd moved to usbterm stephan 2011-12-09 09:46:55 +00:00
  • 3068279c98 in scope readout mode, only read nsums samples stephan 2011-12-09 09:45:41 +00:00
  • 7791d044ee do not ADC_SAMPLE_EARLY, to cover the long SCK->DOUT roundtrip stephan 2011-12-09 09:44:38 +00:00
  • 144c7cdf2f add fifo_halffull (unused) stephan 2011-12-09 09:43:29 +00:00
  • 4b53bbdb5d use fast tokens for extended deadtime stephan 2011-12-09 09:40:03 +00:00
  • ec24caf68d starline fix stephan 2011-12-07 20:30:08 +00:00
  • 7bbad66397 encode first variable width version nixdorf 2011-12-07 17:00:23 +00:00
  • bd26b4d31b Makefile added nixdorf 2011-12-07 13:30:16 +00:00
  • f3fc802f12 starline: add y multiplier (float) stephan 2011-12-07 01:22:16 +00:00
  • 70e5c150d9 starline: add multiplier input register stephan 2011-12-06 23:12:24 +00:00
  • 67bbf702cf reenable delay based on fast tokens, counting from trigger, not done, fixed stephan 2011-12-06 18:33:36 +00:00
  • 003b6646d1 reenable delay based on fast tokens, counting from trigger, not done stephan 2011-12-06 18:18:42 +00:00
  • 3c3f1101f9 warnings moved from fifo_halffull stephan 2011-12-06 18:17:44 +00:00
  • bc58773102 Moved files from martins computer kruse 2011-12-06 15:20:24 +00:00
  • a252b7b398 starfinder: starline module simulates fine stephan 2011-12-06 09:03:19 +00:00
  • b88c481f5d idef-x parser stephan 2011-12-05 19:24:07 +00:00
  • 19b051e114 pirena data parser stephan 2011-12-05 16:44:17 +00:00
  • 5daaf8dc24 add menable command stephan 2011-12-05 09:54:30 +00:00
  • 716a5ba4f1 add findarena command stephan 2011-12-05 09:53:53 +00:00
  • 7fd5a1890e ccd SRAM interface stephan 2011-12-02 23:03:27 +00:00
  • 923518440b parameter syntax fix for actel stephan 2011-12-02 19:39:52 +00:00
  • 9766febc98 fix virena READ stuck high at empty l2 triggers stephan 2011-12-02 18:26:09 +00:00
  • 1ac9322520 fix testpulser stephan 2011-12-02 18:23:18 +00:00
  • faefc56300 invert TF polarity stephan 2011-12-02 11:13:18 +00:00
  • 9eca8a4c21 invert TF polarity stephan 2011-12-02 11:11:49 +00:00
  • e08f2371f5 add S/C to LA, drop adc_DCO stephan 2011-12-02 11:11:33 +00:00
  • 68585fad73 fix fifo stephan 2011-11-30 19:50:25 +00:00
  • 34024ec30b add uccd.py stephan 2011-11-30 19:50:01 +00:00
  • b66a8f4d1b add CCDRENA flash name stephan 2011-11-30 19:49:49 +00:00
  • 21462b5d17 add VPLOT stephan 2011-11-30 19:49:27 +00:00
  • 48baafc288 arena.py: fix LA mask parser stephan 2011-11-30 19:49:04 +00:00
  • 51a32ead41 renamed findirena to findxrena, removed call stephan 2011-11-30 19:48:25 +00:00
  • 586a80de10 ccd flash fat stephan 2011-11-30 19:47:22 +00:00
  • 429fad5696 ccdsirena: fix sram ce, halffull stephan 2011-11-30 18:15:33 +00:00
  • 171153ef97 add l3 for martin stephan 2011-11-30 15:51:26 +00:00
  • dd5e7a34f4 deleted comment nixdorf 2011-11-30 13:43:16 +00:00
  • 2015b6b018 second step stephan 2011-11-30 13:42:11 +00:00
  • 18e00b07ca first steps stephan 2011-11-30 12:44:24 +00:00
  • 983ea230b9 move logicanalyser, scope to new arena.py module stephan 2011-11-30 10:01:56 +00:00
  • fe29a4b5eb add productid filter to findirena stephan 2011-11-30 10:00:37 +00:00
  • 2a368ce0fa cecederena_v01 checkout stephan 2011-11-29 22:16:16 +00:00
  • 7548f76f94 add cecederena v01 checkout stephan 2011-11-29 21:26:35 +00:00
  • d7e92fc510 fix quarus error with new port syntax stephan 2011-11-29 21:23:50 +00:00
  • 3aab61bf26 varena: finish half-full based priority stephan 2011-11-29 17:29:52 +00:00
  • afe79a2502 add fifo_halffull output to packetfifo, frontend stephan 2011-11-29 17:29:00 +00:00
  • e5b3b1db70 varena: fix LA fifo header, half-full priority half implemented stephan 2011-11-29 17:10:02 +00:00
  • fe8def1329 use real opamp model stephan 2011-11-29 17:09:13 +00:00
  • 8afe00cad2 adc arena icd added stephan 2011-11-29 17:07:15 +00:00
  • 3841f60e0b ccddriver: pinout fixed and verified stephan 2011-11-28 23:16:20 +00:00
  • b8f99b033f cecederena: fix adc output pins on clk input locs stephan 2011-11-28 23:10:17 +00:00
  • 759c26b04f add pll240(d) VHDL files stephan 2011-11-28 22:07:37 +00:00
  • f2bcf5ff98 cecederena pinout verified stephan 2011-11-28 19:55:37 +00:00
  • 2ee6ac6c8d virena: new VARENA_ADDR stephan 2011-11-28 13:20:16 +00:00
  • bbc5c5835d varena quartus warnings gold file stephan 2011-11-28 13:07:49 +00:00
  • 3644c3be8a more caps, text stephan 2011-11-28 12:42:53 +00:00
  • f555fc4584 title without frame stephan 2011-11-28 12:35:08 +00:00
  • f49b60168e varena_test fix fifo enable stephan 2011-11-28 11:49:29 +00:00
  • b5f892ec0b /altera/stream/noenable stephan 2011-11-28 11:17:04 +00:00
  • a8ab148c31 add iarena fat name stephan 2011-11-28 11:15:31 +00:00
  • 6d8bc0509d u-idef-x: logic analyser and scope configs, misc stephan 2011-11-28 11:14:51 +00:00
  • 9a6505f6ea invert TRIG polarity stephan 2011-11-28 11:13:56 +00:00
  • 9be4f10939 stream_into_arrays stephan 2011-11-28 11:12:23 +00:00
  • 9a49ab0ba7 pirena: merge Lauris changes stephan 2011-11-28 10:44:40 +00:00
  • 516e666e68 pirena: extgen commands stephan 2011-11-28 09:46:34 +00:00
  • a656ec93c7 cecederena: drc clean. LTRX[12] added stephan 2011-11-27 20:46:26 +00:00
  • 00f888ee21 cecederena: drc clean. sRAM caps added stephan 2011-11-27 20:09:00 +00:00