Stephan/solo_altera
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  • 08f3976774 cecederena: drc clean. sRAM caps missing stephan 2011-11-27 19:40:50 +00:00
  • f2ebecbaec cecedcerena: LVS complete stephan 2011-11-27 15:55:07 +00:00
  • 016162f23e cecederena: more LVS stephan 2011-11-27 09:49:06 +00:00
  • 32655763e8 cecederena: schematic matched to layout stephan 2011-11-26 22:45:21 +00:00
  • b99b573437 cecederena: power plane work stephan 2011-11-25 20:53:01 +00:00
  • 10b75b542b varena: changed address map, added logicanalyzer stephan 2011-11-24 20:51:42 +00:00
  • c7ac1ef1a8 sort sample lines behind event lines stephan 2011-11-24 19:51:45 +00:00
  • cb01fcbe30 iarena fix warnings stephan 2011-11-24 08:39:30 +00:00
  • 2c1c29a7ef ix: fix sample the last token stephan 2011-11-23 22:43:08 +00:00
  • bc2ecab803 iarena: invert TRIG pin stephan 2011-11-23 22:42:06 +00:00
  • 3932816c56 cecede: adapter sirena to ccdsirena clock test stephan 2011-11-22 23:10:24 +00:00
  • 06c743adc2 cecederena board stephan 2011-11-22 22:25:59 +00:00
  • 868370f4a7 cecede: serialize ccdclocks stephan 2011-11-22 22:24:44 +00:00
  • bcc8006c42 arena: add spice rules Makefile stephan 2011-11-18 17:32:41 +00:00
  • 9207d547c0 symbols lost+found stephan 2011-11-18 17:17:09 +00:00
  • 25f89671a4 adc128S102_test added stephan 2011-11-18 16:49:26 +00:00
  • 5ccd6f3ae9 cecede: add sram to layout stephan 2011-11-14 18:04:32 +00:00
  • 3ca1f86de2 pirena: fix quartus warnings stephan 2011-11-14 17:58:21 +00:00
  • 3ef94ef4e9 pirena: RBF with trigen, cron scripts stephan 2011-11-14 11:03:42 +00:00
  • 95323db510 pirena: trigger generator stephan 2011-11-14 10:28:46 +00:00
  • ee9d790124 ix: allow for longer acq_time stephan 2011-11-14 07:01:55 +00:00
  • ab86d7b1c6 pirena: trigger generator stephan 2011-11-14 07:00:40 +00:00
  • dc41acde0f iarena fix packet headers stephan 2011-11-11 21:02:12 +00:00
  • 8dcc7ed06c arena_diff spice model stephan 2011-11-11 20:34:15 +00:00
  • 5d07bcac1d iarena: add STROBE to la stephan 2011-11-11 15:17:23 +00:00
  • 19030bd788 compression: rounding fixed, rate plot published for drop=3 stephan 2011-11-09 23:15:06 +00:00
  • 70c675798c compresion: fixing the rounding, ... stephan 2011-11-09 16:17:27 +00:00
  • b9cca0ff6c iarena: add a logic analyser stephan 2011-11-07 07:19:20 +00:00
  • a41e7c74d5 L2 stacks machine format as table stephan 2011-11-07 07:17:09 +00:00
  • e751d8b0ea use acq_time for temp measuremnts as well stephan 2011-11-04 14:42:05 +00:00
  • b2032e2e7e adc128: Makefile stephan 2011-11-04 14:38:12 +00:00
  • 46bf313aeb pirena: ssum regsiter stephan 2011-11-04 14:35:55 +00:00
  • 88d069b2fe iarena update stephan 2011-11-04 14:32:44 +00:00
  • 7a99c345f8 idef-x: add high-level python commands stephan 2011-11-04 14:30:48 +00:00
  • b0bbed584c iarena: use blocking assignement for clk stephan 2011-11-03 09:16:25 +00:00
  • a94b2d7be6 fix warning for unused fifo3 stephan 2011-11-03 09:15:33 +00:00
  • d7872497a6 add io line status, fix threshold readback stephan 2011-11-03 09:15:02 +00:00
  • f82a90f7d0 iarena flash filesystem stephan 2011-11-01 17:16:29 +00:00
  • 3be1fb84fc FPGA docs update, irena L1/L2 stephan 2011-10-27 09:05:47 +00:00
  • 0027cc4779 FPGA docs update stephan 2011-10-26 23:31:52 +00:00
  • 9073e97635 iarena: fix digitalization stephan 2011-10-25 21:54:23 +00:00
  • b3a36c2710 iarena: fix adc pipeline for temp, idef-x model stephan 2011-10-25 20:08:46 +00:00
  • cccc4961d7 iarena: fix sc, temp model stephan 2011-10-24 21:05:46 +00:00
  • 4f43192707 iarena: fix idef-x model stephan 2011-10-24 19:53:21 +00:00
  • bed557727c compression: drop, sept test stephan 2011-10-24 19:51:35 +00:00
  • 97accb59fc adc128: sims support files stephan 2011-10-24 00:05:01 +00:00
  • 2ca95d51e0 adc128: sims pretty good stephan 2011-10-24 00:03:35 +00:00
  • 9e348878cf adc128: about to simplify the cfilter stephan 2011-10-23 23:38:44 +00:00
  • e9c146e2ed adc128: iverilog syntax clean stephan 2011-10-23 12:50:44 +00:00
  • 26bab2584c adc128: scheduler, ... stephan 2011-10-22 19:13:00 +00:00
  • f04da6f047 adc128: going to 16 samples stephan 2011-10-22 12:19:41 +00:00
  • 7f0c3c7c0e adc128 unfinished version with 4xmemblock stephan 2011-10-22 09:02:51 +00:00
  • a497e8fef7 iarena: first sims, all ix reset properly stephan 2011-10-21 13:58:37 +00:00
  • a8066d6721 iarena: first sims, all ix reset properly stephan 2011-10-21 13:58:19 +00:00
  • ed12c04fa8 iarena compiles and synth, no sim yet stephan 2011-10-20 18:37:11 +00:00
  • c384d60e3a ix: cover adc pipeline delay stephan 2011-10-20 06:56:47 +00:00
  • 7a50d15701 adc_test: overview schematic stephan 2011-10-19 21:00:52 +00:00
  • 27df99ea1a idef-x sim model stephan 2011-10-18 20:57:23 +00:00
  • 195f2fa179 ix.v: idef-x cycle engines stephan 2011-10-18 16:49:55 +00:00
  • 3706b4b4bd iarena template compiles and synth stephan 2011-10-17 20:28:53 +00:00
  • b914c96803 copy varena stephan 2011-10-17 19:38:48 +00:00
  • 4ab5572a40 pirena: update pirena commands stephan 2011-10-13 15:42:22 +00:00
  • 01bce374a2 pirena stepper, make value optional stephan 2011-10-13 15:42:00 +00:00
  • f0a0a5a2c1 stepper: fix initial pulse width stephan 2011-10-13 15:14:36 +00:00
  • 45a1114f4e avr spi_slave: do not abort 0xff stephan 2011-10-13 14:35:15 +00:00
  • 8183b55806 Stepper: fix wgm stephan 2011-10-13 14:34:35 +00:00
  • bb5be42b5b arm: implement spi/stepper stephan 2011-10-13 13:24:57 +00:00
  • 9d353a2688 StepperControl: fix Rx return bytes stephan 2011-10-13 12:33:40 +00:00
  • a262dd51dc invert MSB idle bit stephan 2011-10-13 10:58:03 +00:00
  • 94a43d45b6 virena: misc fixes stephan 2011-10-13 09:24:07 +00:00
  • 15b501e3dc StepperControl fix MCU stephan 2011-10-13 09:23:20 +00:00
  • 40a5bf1b2f pirena flash volume name stephan 2011-10-13 09:20:51 +00:00
  • 6e7de5263b pirena: fix build, altera library stephan 2011-10-13 09:19:55 +00:00
  • fcbe1bf6e9 fix misspelled net names stephan 2011-10-13 09:19:24 +00:00
  • 3987ce6c6a pirena: new altera image stephan 2011-10-13 09:18:32 +00:00
  • 6d5c6ec649 varena cron: generic test injection via variable T stephan 2011-10-07 08:25:40 +00:00
  • e21461eaf5 arm virena: add l1timers stephan 2011-10-07 08:24:36 +00:00
  • 1b3d588265 varena: fix vl1trig address conflict stephan 2011-10-07 08:23:44 +00:00
  • 8999c7b810 add uvirena.py stephan 2011-10-06 15:16:04 +00:00
  • 47ecb9c64f arm virena: l2conf l2conf stephan 2011-10-06 15:15:19 +00:00
  • b666e52819 arm: BOX EPTI stephan 2011-10-06 15:14:27 +00:00
  • 0213bbfc62 avr: linker and burn make targets stephan 2011-10-06 15:12:24 +00:00
  • 62ec4e3a75 minor typo s/*/&/ stephan 2011-10-06 13:12:09 +00:00
  • 383ba87bb4 Steppercontrol with 3-byte commands stephan 2011-09-30 13:34:30 +00:00
  • 6ac65b79f4 varena: token_test, fix virena_conf sim stephan 2011-09-30 09:28:45 +00:00
  • d49a3e4a93 varena: force READ stephan 2011-09-27 08:32:55 +00:00
  • d7c68be11e varena: add testpulser stephan 2011-09-27 07:42:11 +00:00
  • 6795b8e674 sirena compression: add sign bit, drop more bits stephan 2011-09-27 07:40:49 +00:00
  • ebeb99d880 sirena compression: change residue definition stephan 2011-09-27 07:39:20 +00:00
  • 6691f886a7 varena: fix virena config command stephan 2011-09-27 07:38:01 +00:00
  • d801b1574d avr spi_slave: sync implementation stephan 2011-09-27 07:35:21 +00:00
  • d0f03b4f44 irena: current shunt resistor values update stephan 2011-09-27 07:33:37 +00:00
  • 5d1a7dd788 virena-ifc: add hama preamp image to connector schematics stephan 2011-09-27 07:32:49 +00:00
  • 93c8ab46e9 pirena: add seldefault register stephan 2011-09-27 07:30:32 +00:00
  • 228a26a510 pirena: mask exttrig by master enable stephan 2011-09-27 07:29:39 +00:00
  • cce16c3c9c ccd: gerber checkout scripts stephan 2011-09-26 18:53:19 +00:00
  • f6ec1a0626 ccd: final touchup of the layout stephan 2011-09-26 18:36:40 +00:00
  • 854f0c3ea2 ccd: bom update stephan 2011-09-26 11:46:20 +00:00
  • 853e1aaaaf ccd: v01 checkout dir stephan 2011-09-26 11:43:21 +00:00
  • 049cee9d86 ccd: more or less done stephan 2011-09-26 11:41:32 +00:00