VERILOG=/usr/local/bin/iverilog
#VERILOG=/usr/bin/iverilog

VERILOGFLAGS = -v -DSIMULATION
%.vvp:
	$(VERILOG) $(VERILOGFLAGS) $($*_FLAGS) -o $@ $^

vcd/%.lxt: %.vvp
	$< -lxt2 | tee $*.log

.PRECIOUS: vcd/%.lxt

VPATH=.:../../altera:../../altera/mega:../../dorn/altera:../../irena/altera/adc128

ahepam_ana_demo.vvp: ahepam_ana_demo.v ahepam_ana_core.v \
 secondcyclone.v serializer.v spififo_sim.v conf_reg.v itof.v \
 packetfifo.v adc128s102.v spififo_sim.v conf_reg.v countbits.v mem.v \
 dorn.v dmem.v divider.v multiply.v \
 pulser.v

ahepam_ana_demo_FLAGS = -sahepam_ana_demo_test -DAHEPAM_ANA_DEMO_TEST \
 -DAHEPAM_ANA_JIG \
 -DINFERRED_SRAM -DSER_FIFO_ALTERA \
 -DWITH_FULL_L1_CONF -DWITH_FULL_L2_CONF -DWITH_FULL_L3_CONF

ahepam_ana_core.vvp: ahepam_ana_core.v \
 secondcyclone.v serializer.v spififo_sim.v conf_reg.v itof.v \
 packetfifo.v adc128s102.v spififo_sim.v conf_reg.v countbits.v mem.v \
 dorn.v dmem.v divider.v multiply.v \
 pulser.v

ahepam_ana_core_FLAGS = -sahepam_ana_core_test -DAHEPAM_ANA_CORE_TEST \
 -DINFERRED_SRAM -DSER_FIFO_ALTERA \
 -DWITH_FULL_L1_CONF -DWITH_FULL_L2_CONF -DWITH_FULL_L3_CONF

MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS))

CYCLONE=3

ifeq ($(CYCLONE),10)
QUARTUS=/usr/local/quartus/intelFPGA_lite/20.1/quartus
else
QUARTUS=/usr/local/quartus/altera13.1/quartus
endif
export PATH:=$(PATH):$(QUARTUS)/bin:.

ifeq ($(CYCLONE),)
%_c3.rbf: %_c3.qsf
	$(MAKE) CYCLONE=3 $@
%_c10.rbf: %_c10.qsf
	$(MAKE) CYCLONE=10 $@
else
%_c$(CYCLONE).qpf: %.qpf
	ln $< $@
%_c$(CYCLONE).sdc: %.sdc
	ln $< $@
endif

QDIR=quartus
$(QDIR)/%.rbf: %.qpf %.qsf %.sdc
	quartus_map $< $(MAPFLGS)
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning $(QDIR)/$*.*.rpt > $*.warnings

$(QDIR)/ahepam_ana_demo_c$(CYCLONE).rbf: ahepam_ana_demo.v ahepam_ana_core.v \
 secondcyclone.v serializer.v spififo.v conf_reg.v itof.v \
 secondcyclone.v serializer.v conf_reg.v itof.v \
 packetfifo.v adc128s102.v spififo_sim.v conf_reg.v countbits.v mem.v \
 dorn.v dmem.v divider.v