export PATH:=$(PATH):.

VERILOG=iverilog

VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
%.vvp:
	$(VERILOG) $(VERILOGFLAGS) -o $@ $^

vcd/%.fst: %.vvp
	$< -fst | tee $*.log

spi_slave.vvp: spi_slave.v spi_slave_test.v spi_master_adc.v spififo_sim.v conf_reg.v
spififo.vvp: spififo_sim.v spififo_sim_test.v
trigger.vvp: trigger.v trigger_test.v spi_slave.v spififo_sim.v conf_reg.v log2.v
conf_reg.vvp: conf_reg.v conf_reg_test.v

serializer_FLAGS = -s serializer_test -DSERIALIZER_TEST
serializer_nopll_FLAGS = $(serializer_FLAGS) -DNO_PLLS
serializer.vvp: serializer.v
serializer_nopll.vvp: serializer.v

SpW.vvp: SpW.v serializer.v
SpW_FLAGS = -DSpW_TEST -sSpW1_test
SpW3.vvp: SpW.v serializer.v
SpW3_FLAGS = -DSpW_TEST -sSpW3_test

lasc.vvp: lasc.v conf_reg.v mega/fifo16.v
lasc_FLAGS = -s lasc_test -DLASC_TEST

utick.vvp: utick.v
utick_FLAGS = -s utick_test -DUTICK_TEST

pll192.vvp: pll192_sim.v pll192_test.v
pll192_FLAGS = -s pll192_test -DPLL192_TEST

slow_clock.vvp: slow_clock.v
slow_clock_FLAGS = -s sclk_to_fclk_test -DSCLK_TO_FCLK_TEST

i2c.vvp: i2c.v
i2c_FLAGS = -s i2c_test -DI2C_TEST
i2cm.vvp: i2c.v spififo_sim.v
i2cm_FLAGS = -s i2cm_test -DI2CM_TEST