quartus/tarena.asm.rpt:Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
quartus/tarena.fit.rpt:  5. I/O Assignment Warnings
quartus/tarena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
quartus/tarena.fit.rpt:; I/O Assignment Warnings                         ;
quartus/tarena.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/tarena.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
quartus/tarena.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
quartus/tarena.fit.rpt:Warning (176674): Following 10 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
quartus/tarena.fit.rpt:    Warning (176118): Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
quartus/tarena.fit.rpt:    Warning (176118): Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
quartus/tarena.fit.rpt:    Warning (176118): Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
quartus/tarena.fit.rpt:    Warning (176118): Pin "adc_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "adc_clk(n)"
quartus/tarena.fit.rpt:    Warning (176118): Pin "ARx[3]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[3](n)"
quartus/tarena.fit.rpt:    Warning (176118): Pin "ARx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[1](n)"
quartus/tarena.fit.rpt:    Warning (176118): Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
quartus/tarena.fit.rpt:    Warning (176118): Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
quartus/tarena.fit.rpt:    Warning (176118): Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
quartus/tarena.fit.rpt:    Warning (176118): Pin "ARx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARx[2](n)"
quartus/tarena.fit.rpt:Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/tarena.fit.rpt:Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/tarena.fit.rpt:Warning (169064): Following 14 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
quartus/tarena.fit.rpt:Info: Quartus II 32-bit Fitter was successful. 0 errors, 17 warnings
quartus/tarena.map.rpt:; temp_adc_values ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; too_fast       ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; too_few        ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; too_many       ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; too_many_small ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; too_many_large ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; too_many_bg    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; lss_init       ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; lss_put        ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; lss_submit     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; timeouts       ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; DEBUG          ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; n      ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; DIN        ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; STROBE     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; go   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; monitor  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; STROBEn ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:; hss     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/tarena.map.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../stein/altera/stein_adc_controller.v(9)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../stein/altera/stein_ix_controller.v(473)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../stein/altera/stein_ix_controller.v(475)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../stein/altera/stein_ix_controller.v(477)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../stein/altera/stein_ix_controller.v(492)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../stein/altera/stein_ix_controller.v(549)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/serializer.v(188)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(13)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(15)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(63)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(106)
quartus/tarena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(120)
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at countbits.v(24): Parameter Declaration in module "countbits" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at tarena.v(75): Parameter Declaration in module "tarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at tarena.v(76): Parameter Declaration in module "tarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at tarena.v(77): Parameter Declaration in module "tarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at tarena.v(78): Parameter Declaration in module "tarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at tarena.v(79): Parameter Declaration in module "tarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at tarena.v(133): Parameter Declaration in module "tarena" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ix.v(229): Parameter Declaration in module "ix_slow_control" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ix.v(230): Parameter Declaration in module "ix_slow_control" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at barrel.v(9): Parameter Declaration in module "barrel" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at priority_encoder.v(8): Parameter Declaration in module "priority_encode" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stein_ix_controller.v(482): Parameter Declaration in module "stein_ix_slow_control" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stein_ix_controller.v(483): Parameter Declaration in module "stein_ix_slow_control" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at arena.v(235): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at arena.v(342): truncated value with size 32 to match size of target (16)
quartus/tarena.map.rpt:Warning (10034): Output port "debug[4..6]" at arena.v(80) has no driver
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(256): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(258): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(71): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(152): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(173): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10034): Output port "hss" at tarena.v(53) has no driver
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_master_adc.v(99): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc_data.v(27): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at oscilloscope.v(78): truncated value with size 32 to match size of target (12)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at oscilloscope.v(140): truncated value with size 32 to match size of target (16)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at logicanalyser.v(74): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at logicanalyser.v(97): truncated value with size 32 to match size of target (16)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(60): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(62): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(64): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(80): truncated value with size 32 to match size of target (20)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at testpulser.v(100): truncated value with size 32 to match size of target (15)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at tarena.v(358): truncated value with size 5 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at tarena.v(391): truncated value with size 32 to match size of target (16)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(343): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(345): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(364): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(366): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(368): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(250): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(252): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(273): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(275): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(283): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_adc_controller.v(75): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(163): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at priority_encoder.v(15): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(972): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(974): truncated value with size 32 to match size of target (2)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1012): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1061): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1068): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1076): truncated value with size 32 to match size of target (5)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1081): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1092): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1094): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1107): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1113): truncated value with size 32 to match size of target (11)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1175): truncated value with size 32 to match size of target (6)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1178): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1180): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1225): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(1248): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at ix.v(521): truncated value with size 32 to match size of target (12)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at tarena.v(464): truncated value with size 32 to match size of target (8)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at tarena.v(471): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(261): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(263): truncated value with size 32 to match size of target (7)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(274): truncated value with size 32 to match size of target (3)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(294): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(296): truncated value with size 32 to match size of target (10)
quartus/tarena.map.rpt:Warning (10230): Verilog HDL assignment warning at stein_ix_controller.v(303): truncated value with size 32 to match size of target (4)
quartus/tarena.map.rpt:Warning (14284): Synthesized away the following node(s):
quartus/tarena.map.rpt:    Warning (14285): Synthesized away the following RAM node(s):
quartus/tarena.map.rpt:        Warning (14320): Synthesized away node "tarena:core|logicanalyser:lana|spififo:buffer|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[14]"
quartus/tarena.map.rpt:        Warning (14320): Synthesized away node "tarena:core|oscilloscope:scope|spififo:buffer|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15]"
quartus/tarena.map.rpt:Warning (12241): 8 hierarchies have connectivity warnings - see the Connectivity Checks report folder
quartus/tarena.map.rpt:Warning (13034): The following nodes have both tri-state and non-tri-state drivers
quartus/tarena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "AC[0]" and its non-tri-state driver.
quartus/tarena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "AC[1]" and its non-tri-state driver.
quartus/tarena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "AC[2]" and its non-tri-state driver.
quartus/tarena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "AC[3]" and its non-tri-state driver.
quartus/tarena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "AC[4]" and its non-tri-state driver.
quartus/tarena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "AC[6]" and its non-tri-state driver.
quartus/tarena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "AC[7]" and its non-tri-state driver.
quartus/tarena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "AC[8]" and its non-tri-state driver.
quartus/tarena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "AC[11]" and its non-tri-state driver.
quartus/tarena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "AC[12]" and its non-tri-state driver.
quartus/tarena.map.rpt:Warning (13039): The following bidir pins have no drivers
quartus/tarena.map.rpt:    Warning (13040): Bidir "AC[5]" has no driver
quartus/tarena.map.rpt:    Warning (13040): Bidir "AC[9]" has no driver
quartus/tarena.map.rpt:    Warning (13040): Bidir "AC[10]" has no driver
quartus/tarena.map.rpt:    Warning (13040): Bidir "adc_mode" has no driver
quartus/tarena.map.rpt:Warning (13009): TRI or OPNDRN buffers permanently enabled
quartus/tarena.map.rpt:    Warning (13010): Node "AC[0]~synth"
quartus/tarena.map.rpt:    Warning (13010): Node "AC[1]~synth"
quartus/tarena.map.rpt:    Warning (13010): Node "AC[2]~synth"
quartus/tarena.map.rpt:    Warning (13010): Node "AC[3]~synth"
quartus/tarena.map.rpt:    Warning (13010): Node "AC[4]~synth"
quartus/tarena.map.rpt:    Warning (13010): Node "AC[6]~synth"
quartus/tarena.map.rpt:    Warning (13010): Node "AC[7]~synth"
quartus/tarena.map.rpt:    Warning (13010): Node "AC[8]~synth"
quartus/tarena.map.rpt:    Warning (13010): Node "AC[11]~synth"
quartus/tarena.map.rpt:    Warning (13010): Node "AC[12]~synth"
quartus/tarena.map.rpt:Warning (13024): Output pins are stuck at VCC or GND
quartus/tarena.map.rpt:    Warning (13410): Pin "debug[6]" is stuck at GND
quartus/tarena.map.rpt:    Warning (13410): Pin "debug[5]" is stuck at GND
quartus/tarena.map.rpt:    Warning (13410): Pin "debug[4]" is stuck at GND
quartus/tarena.map.rpt:    Warning (13410): Pin "debug[3]" is stuck at GND
quartus/tarena.map.rpt:    Warning (13410): Pin "debug[1]" is stuck at GND
quartus/tarena.map.rpt:Warning (15899): PLL "pll96:pll0|altpll:altpll_component|altpll_lm43:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
quartus/tarena.map.rpt:Warning (21074): Design contains 6 input pin(s) that do not drive logic
quartus/tarena.map.rpt:    Warning (15610): No output dependent on input pin "clk_T1"
quartus/tarena.map.rpt:    Warning (15610): No output dependent on input pin "trigger"
quartus/tarena.map.rpt:    Warning (15610): No output dependent on input pin "Rx[4]"
quartus/tarena.map.rpt:    Warning (15610): No output dependent on input pin "Rx[3]"
quartus/tarena.map.rpt:    Warning (15610): No output dependent on input pin "ARx[3]"
quartus/tarena.map.rpt:    Warning (15610): No output dependent on input pin "ARx[1]"
quartus/tarena.map.rpt:Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 134 warnings
quartus/tarena.sta.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/tarena.sta.rpt:Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning