VERILOG=/usr/local/bin/iverilog
#VERILOG=/usr/bin/iverilog

VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
%.vvp:
	$(VERILOG) $(VERILOGFLAGS) -o $@ $^

vcd/%.lxt: %.vvp
	$< -lxt2 | tee $*.log

.PRECIOUS: vcd/%.lxt vcd/%.vcd

VPATH=.:../../altera:../../altera/mega:../../arena/altera

ccdclocks_FLAGS = -DCCDCLOCKS_TEST -s ccdclocks_test
ccdclocks.vvp: ccdclocks.v conf_reg.v
starfinder.vvp: starfinder.v conf_reg.v

ccddriver.vvp: ccddriver.v conf_reg.v spififo_sim.v spi_master_adc.v \
	serializer.v starfinder.v ccdclocks.v ad9251_data.v

CECEDERENA_SOURCES = cecederena.v fprojection.v \
	conf_reg.v spififo_sim.v spi_master_adc.v \
	serializer.v ccddriver.v starfinder.v ccdclocks.v \
	frontend.v countbits.v frontend_test.v spi_slave.v spififo_sim.v \
        conf_reg.v packetfifo.v logicanalyser.v \
	ad9649.v secondcyclone.v cypress.v ad9251_data.v

cecederena.vvp: $(CECEDERENA_SOURCES) 

ccdimage.vvp: $(CECEDERENA_SOURCES)

cypress_FLAGS = -DCYPRESS_TEST
starfinder_FLAGS = -DSTARFINDER_TEST
ccdimage_FLAGS = -DCECEDERENA_TEST -s cecederena_test -DSER_FIFO_ALTERA
cecederena_FLAGS = $(ccdimage_FLAGS) -DWITH_STARFINDER

QUARTUS=/usr/local/quartus/altera9.1sp1/quartus
export PATH:=$(PATH):$(QUARTUS)/bin

MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS))

default: cecederena.rbf starimag.rbf starfind.rbf

starfind.rbf: ccddriver.v conf_reg.v spi_master_adc.v spififo.v \
       secondcyclone.v serializer.v \
       starfinder.v ccdclocks.v
	/bin/rm -f ccddriver.rbf
	$(MAKE) ccddriver_MAPDEFS=WITH_STARFINDER=1 ccddriver.rbf
	/bin/mv ccddriver.rbf $@
	/bin/mv ccddriver.warnings starfind.warnings

starimag.rbf: ccddriver.rbf
	/bin/mv $< $@
	/bin/mv ccddriver.warnings starimag.warnings

%.rbf: %.qpf %.qsf %.sdc %.v 
	quartus_map $< $(MAPFLGS)
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning $*.*.rpt | grep -v 'truncated value with size 32 ' > $*.warnings

ccddriver.rbf: conf_reg.v spi_master_adc.v spififo.v \
       secondcyclone.v serializer.v \
       starfinder.v ccdclocks.v ad9251_data.v
cecederena.rbf: frontend.v packetfifo.v conf_reg.v \
       spififo.v pll240.vhd pll240d.vhd \
       secondcyclone.v spi_slave.v serializer.v \
       cypress.v fprojection.v