V=v1

#VERILOG=/usr/local/bin/iverilog
VERILOG=/usr/bin/iverilog

VERILOGFLAGS = -v -Wall -Wno-timescale -DSIMULATION $($*_FLAGS)
%.vvp:
	-grep TODO $(filter %.v,$^) > TODO.$*
	$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v,$^)

vcd/%.lxt: %.vvp
	$< -lxt2 | tee $*.log

.PRECIOUS: vcd/%.lxt

VPATH=../../altera:../../altera/mega:../../hetept/altera:\
../../irena/altera/adc128:../../irena/altera/direna:\
../../sirena/altera:../../nm64/altera

rpirena_FLAGS = -srpirena_test -DIRENACORE -DRPIRENA_TEST -DNOHALFCLK -DWITH_SPI_SSEL \
 -DHAVE_ABT2F -DINFERRED_SRAM -DTWOTHR -DI2CM
rpirena.vvp:  rpirena.v i2c.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v \
 frontend_test.v  fifo8_sim.v hkadc.v adc128s102.v pulser.v \
 filter.v sfilter.v irena_core.v adccntl.v itof.v \
 direna_test.v serializer.v countbits.v mem.v nmcounter.v

ifeq ($V,10)
QUARTUS=/usr/local/quartus/intelFPGA_lite/20.1/quartus
else
QUARTUS=/usr/local/quartus/altera13.1/quartus
#QUARTUS=/usr/local/quartus/altera9.1sp1/quartus
endif
export PATH:=$(PATH):$(QUARTUS)/bin

QDIR=quartus
$(QDIR)/%.rbf: %.qpf %.qsf %.sdc
	quartus_map $<
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning $(QDIR)/$*.*.rpt > $*.warnings

FRONTEND = conf_reg.v spi_slave.v pll384.v spififo.v frontend.v packetfifo.v
HKADC = hkadc.v adc128s102.v
IRENA = filter.v sfilter.v irena_core.v adccntl.v itof.v
GSE48 = sologse48.v icucore.v uart.v memory.v secondcyclone.v serializer.v

$(QDIR)/rpirena.rbf: rpirena.v $(FRONTEND) $(HKADC) $(IRENA) i2c.v
$(QDIR)/rpirena10.rbf: rpirena.v $(FRONTEND) $(HKADC) $(IRENA)

rpigse_FLAGS = -srpigse_test -DRPIGSE_TEST \
  -DSOLOGSE48 -DWITH_SPI_SSEL -DSER_FIFO_ALTERA
rpigse.vvp: rpirena.v sologse48.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
 frontend_test.v  fifo8_sim.v hkadc.v adc128s102.v \
 icucore.v uart.v memory.v secondcyclone.v serializer.v

$(QDIR)/rpigse.rbf: rpirena.v $(FRONTEND) $(HKADC) $(GSE48)