quartus/rpirena.asm.rpt:Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
quartus/rpirena.fit.rpt:  5. I/O Assignment Warnings
quartus/rpirena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
quartus/rpirena.fit.rpt:; I/O Assignment Warnings                         ;
quartus/rpirena.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/rpirena.fit.rpt:Warning (15901): PLL "pll384:pll0|altpll:altpll_component|altpll_r273:auto_generated|pll1" has parameter clk0_counter set to C0 specified but port CLK[0] is not connected
quartus/rpirena.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
quartus/rpirena.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
quartus/rpirena.fit.rpt:Warning (176674): Following 4 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
quartus/rpirena.fit.rpt:    Warning (176118): Pin "LRx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRx[2](n)"
quartus/rpirena.fit.rpt:    Warning (176118): Pin "LRTx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRTx[2](n)"
quartus/rpirena.fit.rpt:    Warning (176118): Pin "LRTx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRTx[1](n)"
quartus/rpirena.fit.rpt:    Warning (176118): Pin "LRx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRx[1](n)"
quartus/rpirena.fit.rpt:Warning (176251): Ignoring some wildcard destinations of fast I/O register assignments
quartus/rpirena.fit.rpt:Warning (169177): 41 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
quartus/rpirena.fit.rpt:Warning (169203): PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447.
quartus/rpirena.fit.rpt:Warning (169064): Following 27 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
quartus/rpirena.fit.rpt:Info: Quartus II 32-bit Fitter was successful. 0 errors, 13 warnings
quartus/rpirena.map.rpt:; collision  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; bus_active ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; its_me     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; sdone      ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; svalid     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; scollision ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; saddr      ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; sread      ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; start_bit  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; stop_bit   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; qs         ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; CSn   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; SCLKn ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; dout1 ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; dine  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; n     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; rro  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; nsamples ; Input ; Warning  ; Input port expression (10 bits) is wider than the input port (8 bits) it drives.  The 2 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
quartus/rpirena.map.rpt:; rbusy ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; empty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; rro        ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; a          ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; b          ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; apeak      ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; bzero      ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; fsiz1      ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; fmatch1    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; conf3          ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; fifo_empty     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; attn           ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; c1     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:; c4     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena.map.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/rpirena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../hetept/altera/hkadc.v(9)
quartus/rpirena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../hetept/altera/hkadc.v(30)
quartus/rpirena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(13)
quartus/rpirena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(15)
quartus/rpirena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(63)
quartus/rpirena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(106)
quartus/rpirena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(120)
quartus/rpirena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../irena/altera/adc128/sfilter.v(443)
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(41): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(42): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(43): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(44): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(45): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(46): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(47): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(55): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(56): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(57): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(58): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(86): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(87): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(88): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(89): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(91): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(92): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at adccntl.v(140): Parameter Declaration in module "adc_channels" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(215): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at sfilter.v(899): Parameter Declaration in module "trigger" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ms5540c.v(130): Parameter Declaration in module "ms5540c" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/rpirena.map.rpt:Warning (10027): Verilog HDL or VHDL warning at the rpirena.v(190): index expression is not wide enough to address all of the elements in the array
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at rpirena.v(317): truncated value with size 32 to match size of target (27)
quartus/rpirena.map.rpt:Warning (10034): Output port "LTxP[2]" at rpirena.v(23) has no driver
quartus/rpirena.map.rpt:Warning (10034): Output port "LTxN[2]" at rpirena.v(24) has no driver
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(256): truncated value with size 32 to match size of target (8)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(258): truncated value with size 32 to match size of target (8)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(71): truncated value with size 32 to match size of target (3)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(152): truncated value with size 32 to match size of target (10)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(173): truncated value with size 32 to match size of target (10)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (5)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (10)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at irena_core.v(82): truncated value with size 32 to match size of target (16)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at irena_core.v(199): truncated value with size 32 to match size of target (8)
quartus/rpirena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at adccntl.v(116): object "phmm" assigned a value but never read
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at adccntl.v(118): truncated value with size 32 to match size of target (6)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(910): truncated value with size 32 to match size of target (7)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(948): truncated value with size 32 to match size of target (6)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(968): truncated value with size 32 to match size of target (10)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1715): truncated value with size 32 to match size of target (7)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1720): truncated value with size 32 to match size of target (7)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1737): truncated value with size 30 to match size of target (16)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1078): truncated value with size 32 to match size of target (4)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1105): truncated value with size 32 to match size of target (4)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1107): truncated value with size 32 to match size of target (4)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1136): truncated value with size 32 to match size of target (16)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1189): truncated value with size 32 to match size of target (16)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1205): truncated value with size 32 to match size of target (8)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1228): truncated value with size 32 to match size of target (4)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1233): truncated value with size 32 to match size of target (4)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1284): truncated value with size 32 to match size of target (4)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1326): truncated value with size 32 to match size of target (8)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1333): truncated value with size 32 to match size of target (6)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1335): truncated value with size 32 to match size of target (6)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1344): truncated value with size 32 to match size of target (2)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(829): truncated value with size 32 to match size of target (5)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(832): truncated value with size 32 to match size of target (5)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(169): truncated value with size 32 to match size of target (17)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(220): truncated value with size 32 to match size of target (6)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(222): truncated value with size 32 to match size of target (6)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(304): truncated value with size 32 to match size of target (16)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(21): truncated value with size 32 to match size of target (6)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(24): truncated value with size 32 to match size of target (6)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(27): truncated value with size 32 to match size of target (4)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(28): truncated value with size 32 to match size of target (30)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(39): truncated value with size 30 to match size of target (12)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at hkadc.v(55): truncated value with size 32 to match size of target (3)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(163): truncated value with size 32 to match size of target (4)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(134): truncated value with size 32 to match size of target (11)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(136): truncated value with size 32 to match size of target (11)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(149): truncated value with size 32 to match size of target (12)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(159): truncated value with size 32 to match size of target (8)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(206): truncated value with size 32 to match size of target (5)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (16)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at rpirena.v(375): truncated value with size 32 to match size of target (7)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at i2c.v(537): truncated value with size 32 to match size of target (18)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at i2c.v(61): truncated value with size 4 to match size of target (3)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at i2c.v(62): truncated value with size 4 to match size of target (3)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at i2c.v(88): truncated value with size 32 to match size of target (10)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at i2c.v(97): truncated value with size 32 to match size of target (10)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at i2c.v(190): truncated value with size 32 to match size of target (4)
quartus/rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at i2c.v(268): truncated value with size 32 to match size of target (4)
quartus/rpirena.map.rpt:Warning (12241): 10 hierarchies have connectivity warnings - see the Connectivity Checks report folder
quartus/rpirena.map.rpt:Warning (13034): The following nodes have both tri-state and non-tri-state drivers
quartus/rpirena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "PP[0]" and its non-tri-state driver.
quartus/rpirena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "PP[1]" and its non-tri-state driver.
quartus/rpirena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "PP[2]" and its non-tri-state driver.
quartus/rpirena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "PP[3]" and its non-tri-state driver.
quartus/rpirena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "PP[4]" and its non-tri-state driver.
quartus/rpirena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "PP[5]" and its non-tri-state driver.
quartus/rpirena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "EE[4]" and its non-tri-state driver.
quartus/rpirena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "EE[5]" and its non-tri-state driver.
quartus/rpirena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "EE[6]" and its non-tri-state driver.
quartus/rpirena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "EE[7]" and its non-tri-state driver.
quartus/rpirena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "EE[8]" and its non-tri-state driver.
quartus/rpirena.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "EE[9]" and its non-tri-state driver.
quartus/rpirena.map.rpt:Warning (13039): The following bidir pins have no drivers
quartus/rpirena.map.rpt:    Warning (13040): Bidir "EE[10]" has no driver
quartus/rpirena.map.rpt:    Warning (13040): Bidir "gpio17" has no driver
quartus/rpirena.map.rpt:    Warning (13040): Bidir "gpio22" has no driver
quartus/rpirena.map.rpt:    Warning (13040): Bidir "gpio27" has no driver
quartus/rpirena.map.rpt:    Warning (13040): Bidir "gpclk0" has no driver
quartus/rpirena.map.rpt:    Warning (13040): Bidir "SCL" has no driver
quartus/rpirena.map.rpt:    Warning (13040): Bidir "SDA" has no driver
quartus/rpirena.map.rpt:    Warning (13040): Bidir "DD[0]" has no driver
quartus/rpirena.map.rpt:    Warning (13040): Bidir "DD[1]" has no driver
quartus/rpirena.map.rpt:    Warning (13040): Bidir "DD[2]" has no driver
quartus/rpirena.map.rpt:    Warning (13040): Bidir "DD[3]" has no driver
quartus/rpirena.map.rpt:    Warning (13040): Bidir "DD[4]" has no driver
quartus/rpirena.map.rpt:    Warning (13040): Bidir "LL[0]" has no driver
quartus/rpirena.map.rpt:    Warning (13040): Bidir "LL[3]" has no driver
quartus/rpirena.map.rpt:    Warning (13040): Bidir "LL[4]" has no driver
quartus/rpirena.map.rpt:Warning (13009): TRI or OPNDRN buffers permanently enabled
quartus/rpirena.map.rpt:    Warning (13010): Node "PP[0]~synth"
quartus/rpirena.map.rpt:    Warning (13010): Node "PP[1]~synth"
quartus/rpirena.map.rpt:    Warning (13010): Node "PP[2]~synth"
quartus/rpirena.map.rpt:    Warning (13010): Node "PP[3]~synth"
quartus/rpirena.map.rpt:    Warning (13010): Node "PP[4]~synth"
quartus/rpirena.map.rpt:    Warning (13010): Node "PP[5]~synth"
quartus/rpirena.map.rpt:    Warning (13010): Node "EE[4]~synth"
quartus/rpirena.map.rpt:    Warning (13010): Node "EE[5]~synth"
quartus/rpirena.map.rpt:    Warning (13010): Node "EE[6]~synth"
quartus/rpirena.map.rpt:    Warning (13010): Node "EE[7]~synth"
quartus/rpirena.map.rpt:    Warning (13010): Node "EE[8]~synth"
quartus/rpirena.map.rpt:    Warning (13010): Node "EE[9]~synth"
quartus/rpirena.map.rpt:Warning (13024): Output pins are stuck at VCC or GND
quartus/rpirena.map.rpt:    Warning (13410): Pin "LTxP[2]" is stuck at GND
quartus/rpirena.map.rpt:    Warning (13410): Pin "LTxN[2]" is stuck at GND
quartus/rpirena.map.rpt:Warning (15901): PLL "pll384:pll0|altpll:altpll_component|altpll_r273:auto_generated|pll1" has parameter clk0_counter set to C0 specified but port CLK[0] is not connected
quartus/rpirena.map.rpt:Warning (21074): Design contains 6 input pin(s) that do not drive logic
quartus/rpirena.map.rpt:    Warning (15610): No output dependent on input pin "spi_cs[1]"
quartus/rpirena.map.rpt:    Warning (15610): No output dependent on input pin "LRx[2]"
quartus/rpirena.map.rpt:    Warning (15610): No output dependent on input pin "LRTx[2]"
quartus/rpirena.map.rpt:    Warning (15610): No output dependent on input pin "LRTx[1]"
quartus/rpirena.map.rpt:    Warning (15610): No output dependent on input pin "CC[0]"
quartus/rpirena.map.rpt:    Warning (15610): No output dependent on input pin "CC[2]"
quartus/rpirena.map.rpt:Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 147 warnings
quartus/rpirena.sta.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/rpirena.sta.rpt:Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning