quartus/rpirena10.asm.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
quartus/rpirena10.asm.rpt:Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
quartus/rpirena10.fit.rpt: 20. I/O Assignment Warnings
quartus/rpirena10.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings                 ; Off                                   ; Off                                   ;
quartus/rpirena10.fit.rpt:; I/O Assignment Warnings                         ;
quartus/rpirena10.fit.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
quartus/rpirena10.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
quartus/rpirena10.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
quartus/rpirena10.fit.rpt:Warning (176674): Following 4 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
quartus/rpirena10.fit.rpt:    Warning (176118): Pin "LRx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRx[2](n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 22
quartus/rpirena10.fit.rpt:    Warning (176118): Pin "LRTx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRTx[2](n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 25
quartus/rpirena10.fit.rpt:    Warning (176118): Pin "LRTx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRTx[1](n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 25
quartus/rpirena10.fit.rpt:    Warning (176118): Pin "LRx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRx[1](n)" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 22
quartus/rpirena10.fit.rpt:Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 65 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
quartus/rpirena10.fit.rpt:Warning (169177): 39 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone 10 LP Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
quartus/rpirena10.fit.rpt:Warning (169203): PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Intel FPGA requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Intel recommends termination method as specified in the Application Note 447.
quartus/rpirena10.fit.rpt:Warning (169064): Following 26 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
quartus/rpirena10.fit.rpt:Info: Quartus Prime Fitter was successful. 0 errors, 12 warnings
quartus/rpirena10.map.rpt:; CSn   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; SCLKn ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; dout1 ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; dine  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; n     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; rro  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; rbusy ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; empty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; sc_channel ; Output ; Warning  ; Output or bidir port (6 bits) is wider than the port expression (5 bits) it drives; bit(s) "sc_channel[5..5]" have no fanouts ;
quartus/rpirena10.map.rpt:; rro        ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                      ;
quartus/rpirena10.map.rpt:; a          ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; b          ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; apeak      ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; bzero      ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; conf3         ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; fifo_empty    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; attn          ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; c1     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; c2     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; c3     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:; c4     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/rpirena10.map.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
quartus/rpirena10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../hetept/altera/hkadc.v(9) File: /home/blaulicht/stephan/svn@asterix/solo/eda/hetept/altera/hkadc.v Line: 9
quartus/rpirena10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../hetept/altera/hkadc.v(30) File: /home/blaulicht/stephan/svn@asterix/solo/eda/hetept/altera/hkadc.v Line: 30
quartus/rpirena10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(13) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 13
quartus/rpirena10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(15) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 15
quartus/rpirena10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(63) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 63
quartus/rpirena10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(106) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 106
quartus/rpirena10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(120) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 120
quartus/rpirena10.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../irena/altera/adc128/sfilter.v(443) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 443
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(39): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 39
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(40): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 40
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(41): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 41
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(42): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 42
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(43): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 43
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(44): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 44
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(45): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 45
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(53): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 53
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(54): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 54
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(55): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 55
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(56): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 56
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(84): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 84
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(85): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 85
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(86): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 86
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(87): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 87
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(89): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 89
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(90): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 90
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at adccntl.v(140): Parameter Declaration in module "adc_channels" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/adccntl.v Line: 140
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at sfilter.v(899): Parameter Declaration in module "trigger" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 899
quartus/rpirena10.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ms5540c.v(120): Parameter Declaration in module "ms5540c" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/ms5540c.v Line: 120
quartus/rpirena10.map.rpt:Warning (10027): Verilog HDL or VHDL warning at the rpirena.v(187): index expression is not wide enough to address all of the elements in the array File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 187
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at rpirena.v(314): truncated value with size 32 to match size of target (27) File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 314
quartus/rpirena10.map.rpt:Warning (10034): Output port "LTxP[2]" at rpirena.v(23) has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 23
quartus/rpirena10.map.rpt:Warning (10034): Output port "LTxN[2]" at rpirena.v(24) has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 24
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/spi_slave.v Line: 97
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/spi_slave.v Line: 99
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(256): truncated value with size 32 to match size of target (8) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/spi_slave.v Line: 256
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(258): truncated value with size 32 to match size of target (8) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/spi_slave.v Line: 258
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/packetfifo.v Line: 70
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(150): truncated value with size 32 to match size of target (10) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/packetfifo.v Line: 150
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(171): truncated value with size 32 to match size of target (10) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/packetfifo.v Line: 171
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (5) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/countbits.v Line: 13
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (10) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/countbits.v Line: 13
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at irena_core.v(80): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 80
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at irena_core.v(197): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/irena_core.v Line: 197
quartus/rpirena10.map.rpt:Warning (10036): Verilog HDL or VHDL warning at adccntl.v(116): object "phmm" assigned a value but never read File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/adccntl.v Line: 116
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at adccntl.v(118): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/direna/adccntl.v Line: 118
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(910): truncated value with size 32 to match size of target (7) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 910
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(948): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 948
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(968): truncated value with size 32 to match size of target (10) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 968
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1663): truncated value with size 32 to match size of target (7) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1663
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1668): truncated value with size 32 to match size of target (7) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1668
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1685): truncated value with size 30 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1685
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1076): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1076
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1103): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1103
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1105): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1105
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1154): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1154
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1168): truncated value with size 32 to match size of target (8) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1168
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1185): truncated value with size 32 to match size of target (5) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1185
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1187): truncated value with size 32 to match size of target (5) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1187
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1232): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1232
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1274): truncated value with size 32 to match size of target (8) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1274
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1281): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1281
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1283): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1283
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1292): truncated value with size 32 to match size of target (2) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 1292
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(829): truncated value with size 32 to match size of target (5) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 829
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(832): truncated value with size 32 to match size of target (5) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/adc128/sfilter.v Line: 832
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(158): truncated value with size 32 to match size of target (13) File: /home/blaulicht/stephan/svn@asterix/solo/eda/nm64/altera/nmcounter.v Line: 158
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(209): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/nm64/altera/nmcounter.v Line: 209
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(211): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/nm64/altera/nmcounter.v Line: 211
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(293): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/nm64/altera/nmcounter.v Line: 293
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(21): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/itof.v Line: 21
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(24): truncated value with size 32 to match size of target (6) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/itof.v Line: 24
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(27): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/itof.v Line: 27
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(28): truncated value with size 32 to match size of target (30) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/itof.v Line: 28
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(39): truncated value with size 30 to match size of target (12) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/itof.v Line: 39
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at hkadc.v(55): truncated value with size 32 to match size of target (3) File: /home/blaulicht/stephan/svn@asterix/solo/eda/hetept/altera/hkadc.v Line: 55
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(163): truncated value with size 32 to match size of target (4) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/adc128s102.v Line: 163
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(123): truncated value with size 32 to match size of target (11) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/ms5540c.v Line: 123
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(125): truncated value with size 32 to match size of target (11) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/ms5540c.v Line: 125
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(141): truncated value with size 32 to match size of target (8) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/ms5540c.v Line: 141
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(188): truncated value with size 32 to match size of target (5) File: /home/blaulicht/stephan/svn@asterix/solo/eda/irena/altera/ms5540c.v Line: 188
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (16) File: /home/blaulicht/stephan/svn@asterix/solo/eda/altera/countbits.v Line: 13
quartus/rpirena10.map.rpt:Warning (10230): Verilog HDL assignment warning at rpirena.v(336): truncated value with size 32 to match size of target (7) File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 336
quartus/rpirena10.map.rpt:Warning (12241): 7 hierarchies have connectivity warnings - see the Connectivity Checks report folder
quartus/rpirena10.map.rpt:Warning (13034): The following nodes have both tri-state and non-tri-state drivers
quartus/rpirena10.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "PP[0]" and its non-tri-state driver. File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 43
quartus/rpirena10.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "PP[1]" and its non-tri-state driver. File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 43
quartus/rpirena10.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "PP[2]" and its non-tri-state driver. File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 43
quartus/rpirena10.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "PP[3]" and its non-tri-state driver. File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 43
quartus/rpirena10.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "PP[4]" and its non-tri-state driver. File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 43
quartus/rpirena10.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "EE[4]" and its non-tri-state driver. File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 46
quartus/rpirena10.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "EE[5]" and its non-tri-state driver. File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 46
quartus/rpirena10.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "EE[6]" and its non-tri-state driver. File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 46
quartus/rpirena10.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "EE[7]" and its non-tri-state driver. File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 46
quartus/rpirena10.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "EE[8]" and its non-tri-state driver. File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 46
quartus/rpirena10.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "EE[9]" and its non-tri-state driver. File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 46
quartus/rpirena10.map.rpt:Warning (13039): The following bidirectional pins have no drivers
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "gpio17" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 11
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "gpio22" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 12
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "gpio27" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 13
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "gpclk0" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 14
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "SCL" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 16
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "SDA" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 17
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "PP[5]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 43
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "DD[0]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 45
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "DD[1]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 45
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "DD[2]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 45
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "DD[3]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 45
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "LL[0]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 49
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "LL[1]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 49
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "LL[2]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 49
quartus/rpirena10.map.rpt:    Warning (13040): bidirectional pin "LL[3]" has no driver File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 49
quartus/rpirena10.map.rpt:Warning (13009): TRI or OPNDRN buffers permanently enabled
quartus/rpirena10.map.rpt:    Warning (13010): Node "PP[0]~synth" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 43
quartus/rpirena10.map.rpt:    Warning (13010): Node "PP[1]~synth" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 43
quartus/rpirena10.map.rpt:    Warning (13010): Node "PP[2]~synth" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 43
quartus/rpirena10.map.rpt:    Warning (13010): Node "PP[3]~synth" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 43
quartus/rpirena10.map.rpt:    Warning (13010): Node "PP[4]~synth" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 43
quartus/rpirena10.map.rpt:    Warning (13010): Node "EE[4]~synth" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 46
quartus/rpirena10.map.rpt:    Warning (13010): Node "EE[5]~synth" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 46
quartus/rpirena10.map.rpt:    Warning (13010): Node "EE[6]~synth" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 46
quartus/rpirena10.map.rpt:    Warning (13010): Node "EE[7]~synth" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 46
quartus/rpirena10.map.rpt:    Warning (13010): Node "EE[8]~synth" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 46
quartus/rpirena10.map.rpt:    Warning (13010): Node "EE[9]~synth" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 46
quartus/rpirena10.map.rpt:Warning (13024): Output pins are stuck at VCC or GND
quartus/rpirena10.map.rpt:    Warning (13410): Pin "LTxP[2]" is stuck at GND File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 23
quartus/rpirena10.map.rpt:    Warning (13410): Pin "LTxN[2]" is stuck at GND File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 24
quartus/rpirena10.map.rpt:Warning (15899): PLL "pll96:pll0|altpll:altpll_component|altpll_nn43:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/db/altpll_nn43.tdf Line: 28
quartus/rpirena10.map.rpt:Warning (21074): Design contains 5 input pin(s) that do not drive logic
quartus/rpirena10.map.rpt:    Warning (15610): No output dependent on input pin "spi_cs[1]" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 6
quartus/rpirena10.map.rpt:    Warning (15610): No output dependent on input pin "LRx[2]" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 22
quartus/rpirena10.map.rpt:    Warning (15610): No output dependent on input pin "LRTx[2]" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 25
quartus/rpirena10.map.rpt:    Warning (15610): No output dependent on input pin "LRTx[1]" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 25
quartus/rpirena10.map.rpt:    Warning (15610): No output dependent on input pin "CC[0]" File: /home/blaulicht/stephan/svn@asterix/solo/eda/cospi/altera/rpirena.v Line: 44
quartus/rpirena10.map.rpt:Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 134 warnings
quartus/rpirena10.sta.rpt:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
quartus/rpirena10.sta.rpt:Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning