quartus/stis_ana_demo_c3.asm.rpt:Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
quartus/stis_ana_demo_c3.fit.rpt:  5. I/O Assignment Warnings
quartus/stis_ana_demo_c3.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
quartus/stis_ana_demo_c3.fit.rpt:; I/O Assignment Warnings                          ;
quartus/stis_ana_demo_c3.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/stis_ana_demo_c3.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
quartus/stis_ana_demo_c3.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
quartus/stis_ana_demo_c3.fit.rpt:Warning (176674): Following 6 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
quartus/stis_ana_demo_c3.fit.rpt:    Warning (176118): Pin "L_IN[4]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "L_IN[4](n)"
quartus/stis_ana_demo_c3.fit.rpt:    Warning (176118): Pin "L_IN[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "L_IN[1](n)"
quartus/stis_ana_demo_c3.fit.rpt:    Warning (176118): Pin "ARxC" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARxC(n)"
quartus/stis_ana_demo_c3.fit.rpt:    Warning (176118): Pin "L_IN[3]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "L_IN[3](n)"
quartus/stis_ana_demo_c3.fit.rpt:    Warning (176118): Pin "ARxD" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARxD(n)"
quartus/stis_ana_demo_c3.fit.rpt:    Warning (176118): Pin "L_IN[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "L_IN[2](n)"
quartus/stis_ana_demo_c3.fit.rpt:Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/stis_ana_demo_c3.fit.rpt:Warning (176251): Ignoring some wildcard destinations of fast I/O register assignments
quartus/stis_ana_demo_c3.fit.rpt:Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/stis_ana_demo_c3.fit.rpt:Warning (169177): 29 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
quartus/stis_ana_demo_c3.fit.rpt:Warning (169064): Following 14 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
quartus/stis_ana_demo_c3.fit.rpt:Info: Quartus II 32-bit Fitter was successful. 0 errors, 15 warnings
quartus/stis_ana_demo_c3.map.rpt:; a    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; d    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; w    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; pend ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; busy ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; a    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; d    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; w    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; ctick        ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; a    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; d    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; w    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; ctick        ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; RXn    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; fempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; RXn    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; fifof  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; fempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:; lost_sync      ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/stis_ana_demo_c3.map.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/serializer.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(…)
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at multiply.v(…): Parameter Declaration in module "dorn_multiply" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "lsb_encode" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l3" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l3" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l3" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at divider.v(…): Parameter Declaration in module "dorn_divide" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l4" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l4" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l4" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(…): Parameter Declaration in module "dorn_l4" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_slice" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_ana_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at stis_ana_core.v(…): Parameter Declaration in module "stis_split" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(…): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(…): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(…): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(…): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(…): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(…): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/stis_ana_demo_c3.map.rpt:Warning (10034): Output port "L_OUTp[1]" at stis_ana_demo.v(…) has no driver
quartus/stis_ana_demo_c3.map.rpt:Warning (10034): Output port "L_OUTn[1]" at stis_ana_demo.v(…) has no driver
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (7)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (3)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 16 to match size of target (10)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (3)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (7)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 16 to match size of target (7)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (7)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (7)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 16 to match size of target (7)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (4)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (4)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 22 to match size of target (9)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (2)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (4)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(…): truncated value with size 32 to match size of target (5)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(…): truncated value with size 32 to match size of target (5)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (12)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (12)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (12)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (8)
quartus/stis_ana_demo_c3.map.rpt:Warning (10036): Verilog HDL or VHDL warning at dorn.v(…): object "adc_valid" assigned a value but never read
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (3)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 4 to match size of target (3)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (5)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (3)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 5 to match size of target (4)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 6 to match size of target (5)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (2)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 13 to match size of target (12)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(…): truncated value with size 32 to match size of target (2)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(…): truncated value with size 32 to match size of target (4)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (14)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (6)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (4)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (6)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (6)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (4)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (4)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (4)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (4)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (3)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (26)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (12)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 24 to match size of target (12)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 48 to match size of target (12)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 96 to match size of target (12)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 192 to match size of target (12)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (2)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (2)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(…): truncated value with size 26 to match size of target (25)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(…): truncated value with size 26 to match size of target (25)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(…): truncated value with size 32 to match size of target (15)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(…): truncated value with size 26 to match size of target (25)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(…): truncated value with size 26 to match size of target (25)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(…): truncated value with size 32 to match size of target (15)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(…): truncated value with size 16 to match size of target (15)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(…): truncated value with size 32 to match size of target (6)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(…): truncated value with size 32 to match size of target (6)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(…): truncated value with size 32 to match size of target (7)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at log7to4.v(…): truncated value with size 32 to match size of target (5)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at log7to4.v(…): truncated value with size 40 to match size of target (7)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(…): truncated value with size 32 to match size of target (3)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(…): truncated value with size 32 to match size of target (10)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(…): truncated value with size 32 to match size of target (10)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(…): truncated value with size 32 to match size of target (5)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(…): truncated value with size 32 to match size of target (10)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (12)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (12)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at stis_ana_core.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(…): truncated value with size 32 to match size of target (16)
quartus/stis_ana_demo_c3.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(…): truncated value with size 32 to match size of target (2)
quartus/stis_ana_demo_c3.map.rpt:Warning (12241): 8 hierarchies have connectivity warnings - see the Connectivity Checks report folder
quartus/stis_ana_demo_c3.map.rpt:Warning (13034): The following nodes have both tri-state and non-tri-state drivers
quartus/stis_ana_demo_c3.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "AA[15]" and its non-tri-state driver.
quartus/stis_ana_demo_c3.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "AA[14]" and its non-tri-state driver.
quartus/stis_ana_demo_c3.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "AA[13]" and its non-tri-state driver.
quartus/stis_ana_demo_c3.map.rpt:    Warning (13035): Inserted always-enabled tri-state buffer between "AA[9]" and its non-tri-state driver.
quartus/stis_ana_demo_c3.map.rpt:Warning (13039): The following bidir pins have no drivers
quartus/stis_ana_demo_c3.map.rpt:    Warning (13040): Bidir "AA[12]" has no driver
quartus/stis_ana_demo_c3.map.rpt:    Warning (13040): Bidir "AA[11]" has no driver
quartus/stis_ana_demo_c3.map.rpt:    Warning (13040): Bidir "AA[10]" has no driver
quartus/stis_ana_demo_c3.map.rpt:    Warning (13040): Bidir "AA[8]" has no driver
quartus/stis_ana_demo_c3.map.rpt:    Warning (13040): Bidir "AA[7]" has no driver
quartus/stis_ana_demo_c3.map.rpt:    Warning (13040): Bidir "AA[6]" has no driver
quartus/stis_ana_demo_c3.map.rpt:    Warning (13040): Bidir "AA[5]" has no driver
quartus/stis_ana_demo_c3.map.rpt:    Warning (13040): Bidir "debug[3]" has no driver
quartus/stis_ana_demo_c3.map.rpt:    Warning (13040): Bidir "debug[2]" has no driver
quartus/stis_ana_demo_c3.map.rpt:    Warning (13040): Bidir "debug[1]" has no driver
quartus/stis_ana_demo_c3.map.rpt:Warning (13009): TRI or OPNDRN buffers permanently enabled
quartus/stis_ana_demo_c3.map.rpt:    Warning (13010): Node "AA[15]~synth"
quartus/stis_ana_demo_c3.map.rpt:    Warning (13010): Node "AA[14]~synth"
quartus/stis_ana_demo_c3.map.rpt:    Warning (13010): Node "AA[13]~synth"
quartus/stis_ana_demo_c3.map.rpt:    Warning (13010): Node "AA[9]~synth"
quartus/stis_ana_demo_c3.map.rpt:Warning (13024): Output pins are stuck at VCC or GND
quartus/stis_ana_demo_c3.map.rpt:    Warning (13410): Pin "L_OUTp[1]" is stuck at GND
quartus/stis_ana_demo_c3.map.rpt:    Warning (13410): Pin "L_OUTn[1]" is stuck at GND
quartus/stis_ana_demo_c3.map.rpt:    Warning (13410): Pin "A[19]" is stuck at GND
quartus/stis_ana_demo_c3.map.rpt:    Warning (13410): Pin "A[20]" is stuck at GND
quartus/stis_ana_demo_c3.map.rpt:Warning (21074): Design contains 7 input pin(s) that do not drive logic
quartus/stis_ana_demo_c3.map.rpt:    Warning (15610): No output dependent on input pin "GNDs[5]"
quartus/stis_ana_demo_c3.map.rpt:    Warning (15610): No output dependent on input pin "GNDs[4]"
quartus/stis_ana_demo_c3.map.rpt:    Warning (15610): No output dependent on input pin "GNDs[3]"
quartus/stis_ana_demo_c3.map.rpt:    Warning (15610): No output dependent on input pin "GNDs[2]"
quartus/stis_ana_demo_c3.map.rpt:    Warning (15610): No output dependent on input pin "GNDs[1]"
quartus/stis_ana_demo_c3.map.rpt:    Warning (15610): No output dependent on input pin "L_IN[4]"
quartus/stis_ana_demo_c3.map.rpt:    Warning (15610): No output dependent on input pin "L_IN[1]"
quartus/stis_ana_demo_c3.map.rpt:Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 235 warnings
quartus/stis_ana_demo_c3.sta.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/stis_ana_demo_c3.sta.rpt:Critical Warning (332148): Timing requirements not met
quartus/stis_ana_demo_c3.sta.rpt:Critical Warning (332148): Timing requirements not met
quartus/stis_ana_demo_c3.sta.rpt:Critical Warning (332148): Timing requirements not met
quartus/stis_ana_demo_c3.sta.rpt:Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings